528 lines
12 KiB
C
528 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2014 Linaro Ltd.
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* Copyright (c) 2014 HiSilicon Limited.
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*
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* Now only support 7 bit address.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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/* Register Map */
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#define HIX5I2C_CTRL 0x00
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#define HIX5I2C_COM 0x04
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#define HIX5I2C_ICR 0x08
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#define HIX5I2C_SR 0x0c
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#define HIX5I2C_SCL_H 0x10
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#define HIX5I2C_SCL_L 0x14
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#define HIX5I2C_TXR 0x18
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#define HIX5I2C_RXR 0x1c
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/* I2C_CTRL_REG */
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#define I2C_ENABLE BIT(8)
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#define I2C_UNMASK_TOTAL BIT(7)
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#define I2C_UNMASK_START BIT(6)
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#define I2C_UNMASK_END BIT(5)
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#define I2C_UNMASK_SEND BIT(4)
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#define I2C_UNMASK_RECEIVE BIT(3)
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#define I2C_UNMASK_ACK BIT(2)
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#define I2C_UNMASK_ARBITRATE BIT(1)
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#define I2C_UNMASK_OVER BIT(0)
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#define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER)
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/* I2C_COM_REG */
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#define I2C_NO_ACK BIT(4)
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#define I2C_START BIT(3)
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#define I2C_READ BIT(2)
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#define I2C_WRITE BIT(1)
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#define I2C_STOP BIT(0)
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/* I2C_ICR_REG */
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#define I2C_CLEAR_START BIT(6)
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#define I2C_CLEAR_END BIT(5)
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#define I2C_CLEAR_SEND BIT(4)
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#define I2C_CLEAR_RECEIVE BIT(3)
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#define I2C_CLEAR_ACK BIT(2)
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#define I2C_CLEAR_ARBITRATE BIT(1)
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#define I2C_CLEAR_OVER BIT(0)
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#define I2C_CLEAR_ALL (I2C_CLEAR_START | I2C_CLEAR_END | \
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I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
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I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
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I2C_CLEAR_OVER)
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/* I2C_SR_REG */
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#define I2C_BUSY BIT(7)
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#define I2C_START_INTR BIT(6)
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#define I2C_END_INTR BIT(5)
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#define I2C_SEND_INTR BIT(4)
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#define I2C_RECEIVE_INTR BIT(3)
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#define I2C_ACK_INTR BIT(2)
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#define I2C_ARBITRATE_INTR BIT(1)
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#define I2C_OVER_INTR BIT(0)
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enum hix5hd2_i2c_state {
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HIX5I2C_STAT_RW_ERR = -1,
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HIX5I2C_STAT_INIT,
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HIX5I2C_STAT_RW,
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HIX5I2C_STAT_SND_STOP,
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HIX5I2C_STAT_RW_SUCCESS,
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};
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struct hix5hd2_i2c_priv {
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struct i2c_adapter adap;
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struct i2c_msg *msg;
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struct completion msg_complete;
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unsigned int msg_idx;
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unsigned int msg_len;
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int stop;
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void __iomem *regs;
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struct clk *clk;
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struct device *dev;
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spinlock_t lock; /* IRQ synchronization */
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int err;
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unsigned int freq;
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enum hix5hd2_i2c_state state;
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};
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static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c_priv *priv)
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{
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u32 val = readl_relaxed(priv->regs + HIX5I2C_SR);
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writel_relaxed(val, priv->regs + HIX5I2C_ICR);
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return val;
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}
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static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c_priv *priv)
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{
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writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR);
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}
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static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c_priv *priv)
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{
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writel_relaxed(0, priv->regs + HIX5I2C_CTRL);
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}
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static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c_priv *priv)
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{
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writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL,
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priv->regs + HIX5I2C_CTRL);
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}
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static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c_priv *priv)
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{
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u32 rate, val;
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u32 scl, sysclock;
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/* close all i2c interrupt */
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val = readl_relaxed(priv->regs + HIX5I2C_CTRL);
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writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL);
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rate = priv->freq;
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sysclock = clk_get_rate(priv->clk);
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scl = (sysclock / (rate * 2)) / 2 - 1;
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writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H);
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writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L);
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/* restore original interrupt*/
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writel_relaxed(val, priv->regs + HIX5I2C_CTRL);
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dev_dbg(priv->dev, "%s: sysclock=%d, rate=%d, scl=%d\n",
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__func__, sysclock, rate, scl);
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}
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static void hix5hd2_i2c_init(struct hix5hd2_i2c_priv *priv)
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{
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hix5hd2_i2c_disable_irq(priv);
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hix5hd2_i2c_drv_setrate(priv);
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hix5hd2_i2c_clr_all_irq(priv);
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hix5hd2_i2c_enable_irq(priv);
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}
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static void hix5hd2_i2c_reset(struct hix5hd2_i2c_priv *priv)
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{
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clk_disable_unprepare(priv->clk);
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msleep(20);
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clk_prepare_enable(priv->clk);
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hix5hd2_i2c_init(priv);
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}
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static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c_priv *priv)
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{
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unsigned long stop_time;
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u32 int_status;
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/* wait for 100 milli seconds for the bus to be idle */
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stop_time = jiffies + msecs_to_jiffies(100);
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do {
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int_status = hix5hd2_i2c_clr_pend_irq(priv);
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if (!(int_status & I2C_BUSY))
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return 0;
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usleep_range(50, 200);
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} while (time_before(jiffies, stop_time));
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return -EBUSY;
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}
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static void hix5hd2_rw_over(struct hix5hd2_i2c_priv *priv)
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{
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if (priv->state == HIX5I2C_STAT_SND_STOP)
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dev_dbg(priv->dev, "%s: rw and send stop over\n", __func__);
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else
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dev_dbg(priv->dev, "%s: have not data to send\n", __func__);
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priv->state = HIX5I2C_STAT_RW_SUCCESS;
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priv->err = 0;
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}
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static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c_priv *priv)
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{
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if (priv->stop) {
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priv->state = HIX5I2C_STAT_SND_STOP;
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writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM);
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} else {
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hix5hd2_rw_over(priv);
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}
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}
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static void hix5hd2_read_handle(struct hix5hd2_i2c_priv *priv)
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{
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if (priv->msg_len == 1) {
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/* the last byte don't need send ACK */
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writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM);
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} else if (priv->msg_len > 1) {
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/* if i2c master receive data will send ACK */
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writel_relaxed(I2C_READ, priv->regs + HIX5I2C_COM);
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} else {
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hix5hd2_rw_handle_stop(priv);
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}
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}
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static void hix5hd2_write_handle(struct hix5hd2_i2c_priv *priv)
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{
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u8 data;
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if (priv->msg_len > 0) {
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data = priv->msg->buf[priv->msg_idx++];
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writel_relaxed(data, priv->regs + HIX5I2C_TXR);
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writel_relaxed(I2C_WRITE, priv->regs + HIX5I2C_COM);
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} else {
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hix5hd2_rw_handle_stop(priv);
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}
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}
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static int hix5hd2_rw_preprocess(struct hix5hd2_i2c_priv *priv)
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{
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u8 data;
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if (priv->state == HIX5I2C_STAT_INIT) {
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priv->state = HIX5I2C_STAT_RW;
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} else if (priv->state == HIX5I2C_STAT_RW) {
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if (priv->msg->flags & I2C_M_RD) {
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data = readl_relaxed(priv->regs + HIX5I2C_RXR);
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priv->msg->buf[priv->msg_idx++] = data;
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}
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priv->msg_len--;
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} else {
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dev_dbg(priv->dev, "%s: error: priv->state = %d, msg_len = %d\n",
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__func__, priv->state, priv->msg_len);
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return -EAGAIN;
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}
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return 0;
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}
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static irqreturn_t hix5hd2_i2c_irq(int irqno, void *dev_id)
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{
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struct hix5hd2_i2c_priv *priv = dev_id;
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u32 int_status;
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int ret;
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spin_lock(&priv->lock);
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int_status = hix5hd2_i2c_clr_pend_irq(priv);
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/* handle error */
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if (int_status & I2C_ARBITRATE_INTR) {
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/* bus error */
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dev_dbg(priv->dev, "ARB bus loss\n");
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priv->err = -EAGAIN;
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priv->state = HIX5I2C_STAT_RW_ERR;
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goto stop;
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} else if (int_status & I2C_ACK_INTR) {
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/* ack error */
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dev_dbg(priv->dev, "No ACK from device\n");
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priv->err = -ENXIO;
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priv->state = HIX5I2C_STAT_RW_ERR;
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goto stop;
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}
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if (int_status & I2C_OVER_INTR) {
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if (priv->msg_len > 0) {
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ret = hix5hd2_rw_preprocess(priv);
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if (ret) {
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priv->err = ret;
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priv->state = HIX5I2C_STAT_RW_ERR;
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goto stop;
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}
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if (priv->msg->flags & I2C_M_RD)
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hix5hd2_read_handle(priv);
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else
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hix5hd2_write_handle(priv);
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} else {
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hix5hd2_rw_over(priv);
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}
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}
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stop:
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if ((priv->state == HIX5I2C_STAT_RW_SUCCESS &&
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priv->msg->len == priv->msg_idx) ||
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(priv->state == HIX5I2C_STAT_RW_ERR)) {
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hix5hd2_i2c_disable_irq(priv);
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hix5hd2_i2c_clr_pend_irq(priv);
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complete(&priv->msg_complete);
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}
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spin_unlock(&priv->lock);
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return IRQ_HANDLED;
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}
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static void hix5hd2_i2c_message_start(struct hix5hd2_i2c_priv *priv, int stop)
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{
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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hix5hd2_i2c_clr_all_irq(priv);
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hix5hd2_i2c_enable_irq(priv);
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writel_relaxed(i2c_8bit_addr_from_msg(priv->msg),
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priv->regs + HIX5I2C_TXR);
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writel_relaxed(I2C_WRITE | I2C_START, priv->regs + HIX5I2C_COM);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c_priv *priv,
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struct i2c_msg *msgs, int stop)
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{
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unsigned long timeout;
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int ret;
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priv->msg = msgs;
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priv->msg_idx = 0;
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priv->msg_len = priv->msg->len;
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priv->stop = stop;
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priv->err = 0;
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priv->state = HIX5I2C_STAT_INIT;
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reinit_completion(&priv->msg_complete);
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hix5hd2_i2c_message_start(priv, stop);
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timeout = wait_for_completion_timeout(&priv->msg_complete,
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priv->adap.timeout);
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if (timeout == 0) {
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priv->state = HIX5I2C_STAT_RW_ERR;
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priv->err = -ETIMEDOUT;
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dev_warn(priv->dev, "%s timeout=%d\n",
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msgs->flags & I2C_M_RD ? "rx" : "tx",
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priv->adap.timeout);
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}
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ret = priv->state;
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/*
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* If this is the last message to be transfered (stop == 1)
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* Then check if the bus can be brought back to idle.
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|
*/
|
||
|
|
if (priv->state == HIX5I2C_STAT_RW_SUCCESS && stop)
|
||
|
|
ret = hix5hd2_i2c_wait_bus_idle(priv);
|
||
|
|
|
||
|
|
if (ret < 0)
|
||
|
|
hix5hd2_i2c_reset(priv);
|
||
|
|
|
||
|
|
return priv->err;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int hix5hd2_i2c_xfer(struct i2c_adapter *adap,
|
||
|
|
struct i2c_msg *msgs, int num)
|
||
|
|
{
|
||
|
|
struct hix5hd2_i2c_priv *priv = i2c_get_adapdata(adap);
|
||
|
|
int i, ret, stop;
|
||
|
|
|
||
|
|
pm_runtime_get_sync(priv->dev);
|
||
|
|
|
||
|
|
for (i = 0; i < num; i++, msgs++) {
|
||
|
|
stop = (i == num - 1);
|
||
|
|
ret = hix5hd2_i2c_xfer_msg(priv, msgs, stop);
|
||
|
|
if (ret < 0)
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = num;
|
||
|
|
|
||
|
|
out:
|
||
|
|
pm_runtime_mark_last_busy(priv->dev);
|
||
|
|
pm_runtime_put_autosuspend(priv->dev);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static u32 hix5hd2_i2c_func(struct i2c_adapter *adap)
|
||
|
|
{
|
||
|
|
return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct i2c_algorithm hix5hd2_i2c_algorithm = {
|
||
|
|
.master_xfer = hix5hd2_i2c_xfer,
|
||
|
|
.functionality = hix5hd2_i2c_func,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int hix5hd2_i2c_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct device_node *np = pdev->dev.of_node;
|
||
|
|
struct hix5hd2_i2c_priv *priv;
|
||
|
|
unsigned int freq;
|
||
|
|
int irq, ret;
|
||
|
|
|
||
|
|
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||
|
|
if (!priv)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
if (of_property_read_u32(np, "clock-frequency", &freq)) {
|
||
|
|
/* use 100k as default value */
|
||
|
|
priv->freq = I2C_MAX_STANDARD_MODE_FREQ;
|
||
|
|
} else {
|
||
|
|
if (freq > I2C_MAX_FAST_MODE_FREQ) {
|
||
|
|
priv->freq = I2C_MAX_FAST_MODE_FREQ;
|
||
|
|
dev_warn(priv->dev, "use max freq %d instead\n",
|
||
|
|
I2C_MAX_FAST_MODE_FREQ);
|
||
|
|
} else {
|
||
|
|
priv->freq = freq;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
priv->regs = devm_platform_ioremap_resource(pdev, 0);
|
||
|
|
if (IS_ERR(priv->regs))
|
||
|
|
return PTR_ERR(priv->regs);
|
||
|
|
|
||
|
|
irq = platform_get_irq(pdev, 0);
|
||
|
|
if (irq < 0)
|
||
|
|
return irq;
|
||
|
|
|
||
|
|
priv->clk = devm_clk_get(&pdev->dev, NULL);
|
||
|
|
if (IS_ERR(priv->clk)) {
|
||
|
|
dev_err(&pdev->dev, "cannot get clock\n");
|
||
|
|
return PTR_ERR(priv->clk);
|
||
|
|
}
|
||
|
|
clk_prepare_enable(priv->clk);
|
||
|
|
|
||
|
|
strscpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name));
|
||
|
|
priv->dev = &pdev->dev;
|
||
|
|
priv->adap.owner = THIS_MODULE;
|
||
|
|
priv->adap.algo = &hix5hd2_i2c_algorithm;
|
||
|
|
priv->adap.retries = 3;
|
||
|
|
priv->adap.dev.of_node = np;
|
||
|
|
priv->adap.algo_data = priv;
|
||
|
|
priv->adap.dev.parent = &pdev->dev;
|
||
|
|
i2c_set_adapdata(&priv->adap, priv);
|
||
|
|
platform_set_drvdata(pdev, priv);
|
||
|
|
spin_lock_init(&priv->lock);
|
||
|
|
init_completion(&priv->msg_complete);
|
||
|
|
|
||
|
|
hix5hd2_i2c_init(priv);
|
||
|
|
|
||
|
|
ret = devm_request_irq(&pdev->dev, irq, hix5hd2_i2c_irq,
|
||
|
|
IRQF_NO_SUSPEND, dev_name(&pdev->dev), priv);
|
||
|
|
if (ret != 0) {
|
||
|
|
dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", irq);
|
||
|
|
goto err_clk;
|
||
|
|
}
|
||
|
|
|
||
|
|
pm_runtime_set_autosuspend_delay(priv->dev, MSEC_PER_SEC);
|
||
|
|
pm_runtime_use_autosuspend(priv->dev);
|
||
|
|
pm_runtime_set_active(priv->dev);
|
||
|
|
pm_runtime_enable(priv->dev);
|
||
|
|
|
||
|
|
ret = i2c_add_adapter(&priv->adap);
|
||
|
|
if (ret < 0)
|
||
|
|
goto err_runtime;
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
err_runtime:
|
||
|
|
pm_runtime_disable(priv->dev);
|
||
|
|
pm_runtime_set_suspended(priv->dev);
|
||
|
|
err_clk:
|
||
|
|
clk_disable_unprepare(priv->clk);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int hix5hd2_i2c_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev);
|
||
|
|
|
||
|
|
i2c_del_adapter(&priv->adap);
|
||
|
|
pm_runtime_disable(priv->dev);
|
||
|
|
pm_runtime_set_suspended(priv->dev);
|
||
|
|
clk_disable_unprepare(priv->clk);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_PM
|
||
|
|
static int hix5hd2_i2c_runtime_suspend(struct device *dev)
|
||
|
|
{
|
||
|
|
struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev);
|
||
|
|
|
||
|
|
clk_disable_unprepare(priv->clk);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int hix5hd2_i2c_runtime_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev);
|
||
|
|
|
||
|
|
clk_prepare_enable(priv->clk);
|
||
|
|
hix5hd2_i2c_init(priv);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static const struct dev_pm_ops hix5hd2_i2c_pm_ops = {
|
||
|
|
SET_RUNTIME_PM_OPS(hix5hd2_i2c_runtime_suspend,
|
||
|
|
hix5hd2_i2c_runtime_resume,
|
||
|
|
NULL)
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id hix5hd2_i2c_match[] = {
|
||
|
|
{ .compatible = "hisilicon,hix5hd2-i2c" },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, hix5hd2_i2c_match);
|
||
|
|
|
||
|
|
static struct platform_driver hix5hd2_i2c_driver = {
|
||
|
|
.probe = hix5hd2_i2c_probe,
|
||
|
|
.remove = hix5hd2_i2c_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "hix5hd2-i2c",
|
||
|
|
.pm = &hix5hd2_i2c_pm_ops,
|
||
|
|
.of_match_table = hix5hd2_i2c_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
module_platform_driver(hix5hd2_i2c_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Hix5hd2 I2C Bus driver");
|
||
|
|
MODULE_AUTHOR("Wei Yan <sledge.yanwei@huawei.com>");
|
||
|
|
MODULE_LICENSE("GPL");
|
||
|
|
MODULE_ALIAS("platform:hix5hd2-i2c");
|