371 lines
9.1 KiB
C
371 lines
9.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Loongson-2K/Loongson LS7A I2C master mode driver
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*
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* Copyright (C) 2013 Loongson Technology Corporation Limited.
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* Copyright (C) 2014-2017 Lemote, Inc.
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* Copyright (C) 2018-2022 Loongson Technology Corporation Limited.
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*
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* Originally written by liushaozong
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* Rewritten for mainline by Binbin Zhou <zhoubinbin@loongson.cn>
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*/
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#include <linux/bits.h>
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#include <linux/completion.h>
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#include <linux/device.h>
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#include <linux/iopoll.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/units.h>
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/* I2C Registers */
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#define I2C_LS2X_PRER 0x0 /* Freq Division Register(16 bits) */
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#define I2C_LS2X_CTR 0x2 /* Control Register */
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#define I2C_LS2X_TXR 0x3 /* Transport Data Register */
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#define I2C_LS2X_RXR 0x3 /* Receive Data Register */
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#define I2C_LS2X_CR 0x4 /* Command Control Register */
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#define I2C_LS2X_SR 0x4 /* State Register */
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/* Command Control Register Bit */
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#define LS2X_CR_START BIT(7) /* Start signal */
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#define LS2X_CR_STOP BIT(6) /* Stop signal */
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#define LS2X_CR_READ BIT(5) /* Read signal */
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#define LS2X_CR_WRITE BIT(4) /* Write signal */
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#define LS2X_CR_ACK BIT(3) /* Response signal */
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#define LS2X_CR_IACK BIT(0) /* Interrupt response signal */
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/* State Register Bit */
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#define LS2X_SR_NOACK BIT(7) /* Receive NACK */
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#define LS2X_SR_BUSY BIT(6) /* Bus busy state */
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#define LS2X_SR_AL BIT(5) /* Arbitration lost */
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#define LS2X_SR_TIP BIT(1) /* Transmission state */
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#define LS2X_SR_IF BIT(0) /* Interrupt flag */
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/* Control Register Bit */
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#define LS2X_CTR_EN BIT(7) /* 0: I2c frequency setting 1: Normal */
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#define LS2X_CTR_IEN BIT(6) /* Enable i2c interrupt */
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#define LS2X_CTR_MST BIT(5) /* 0: Slave mode 1: Master mode */
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#define CTR_FREQ_MASK GENMASK(7, 6)
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#define CTR_READY_MASK GENMASK(7, 5)
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/* The PCLK frequency from LPB */
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#define LS2X_I2C_PCLK_FREQ (50 * HZ_PER_MHZ)
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/* The default bus frequency, which is an empirical value */
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#define LS2X_I2C_FREQ_STD (33 * HZ_PER_KHZ)
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struct ls2x_i2c_priv {
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struct i2c_adapter adapter;
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void __iomem *base;
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struct i2c_timings i2c_t;
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struct completion cmd_complete;
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};
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/*
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* Interrupt service routine.
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* This gets called whenever an I2C interrupt occurs.
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*/
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static irqreturn_t ls2x_i2c_isr(int this_irq, void *dev_id)
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{
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struct ls2x_i2c_priv *priv = dev_id;
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if (!(readb(priv->base + I2C_LS2X_SR) & LS2X_SR_IF))
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return IRQ_NONE;
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writeb(LS2X_CR_IACK, priv->base + I2C_LS2X_CR);
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complete(&priv->cmd_complete);
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return IRQ_HANDLED;
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}
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/*
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* The ls2x i2c controller supports standard mode and fast mode, so the
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* maximum bus frequency is '400kHz'.
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* The bus frequency is set to the empirical value of '33KHz' by default,
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* but it can also be taken from ACPI or FDT for compatibility with more
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* devices.
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*/
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static void ls2x_i2c_adjust_bus_speed(struct ls2x_i2c_priv *priv)
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{
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struct i2c_timings *t = &priv->i2c_t;
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struct device *dev = priv->adapter.dev.parent;
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u32 acpi_speed = i2c_acpi_find_bus_speed(dev);
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i2c_parse_fw_timings(dev, t, false);
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if (acpi_speed || t->bus_freq_hz)
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t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
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else
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t->bus_freq_hz = LS2X_I2C_FREQ_STD;
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/* Calculate and set i2c frequency. */
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writew(LS2X_I2C_PCLK_FREQ / (5 * t->bus_freq_hz) - 1,
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priv->base + I2C_LS2X_PRER);
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}
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static void ls2x_i2c_init(struct ls2x_i2c_priv *priv)
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{
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/* Set i2c frequency setting mode and disable interrupts. */
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writeb(readb(priv->base + I2C_LS2X_CTR) & ~CTR_FREQ_MASK,
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priv->base + I2C_LS2X_CTR);
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ls2x_i2c_adjust_bus_speed(priv);
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/* Set i2c normal operating mode and enable interrupts. */
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writeb(readb(priv->base + I2C_LS2X_CTR) | CTR_READY_MASK,
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priv->base + I2C_LS2X_CTR);
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}
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static int ls2x_i2c_xfer_byte(struct ls2x_i2c_priv *priv, u8 txdata, u8 *rxdatap)
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{
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u8 rxdata;
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unsigned long time_left;
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writeb(txdata, priv->base + I2C_LS2X_CR);
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time_left = wait_for_completion_timeout(&priv->cmd_complete,
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priv->adapter.timeout);
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if (!time_left)
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return -ETIMEDOUT;
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rxdata = readb(priv->base + I2C_LS2X_SR);
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if (rxdatap)
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*rxdatap = rxdata;
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return 0;
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}
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static int ls2x_i2c_send_byte(struct ls2x_i2c_priv *priv, u8 txdata)
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{
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int ret;
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u8 rxdata;
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ret = ls2x_i2c_xfer_byte(priv, txdata, &rxdata);
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if (ret)
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return ret;
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if (rxdata & LS2X_SR_AL)
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return -EAGAIN;
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if (rxdata & LS2X_SR_NOACK)
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return -ENXIO;
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return 0;
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}
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static int ls2x_i2c_stop(struct ls2x_i2c_priv *priv)
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{
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u8 value;
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writeb(LS2X_CR_STOP, priv->base + I2C_LS2X_CR);
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return readb_poll_timeout(priv->base + I2C_LS2X_SR, value,
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!(value & LS2X_SR_BUSY), 100,
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jiffies_to_usecs(priv->adapter.timeout));
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}
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static int ls2x_i2c_start(struct ls2x_i2c_priv *priv, struct i2c_msg *msgs)
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{
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reinit_completion(&priv->cmd_complete);
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writeb(i2c_8bit_addr_from_msg(msgs), priv->base + I2C_LS2X_TXR);
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return ls2x_i2c_send_byte(priv, LS2X_CR_START | LS2X_CR_WRITE);
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}
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static int ls2x_i2c_rx(struct ls2x_i2c_priv *priv, struct i2c_msg *msg)
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{
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int ret;
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u8 rxdata, *buf = msg->buf;
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u16 len = msg->len;
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/* Contains steps to send start condition and address. */
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ret = ls2x_i2c_start(priv, msg);
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if (ret)
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return ret;
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while (len--) {
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ret = ls2x_i2c_xfer_byte(priv,
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LS2X_CR_READ | (len ? 0 : LS2X_CR_ACK),
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&rxdata);
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if (ret)
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return ret;
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*buf++ = readb(priv->base + I2C_LS2X_RXR);
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}
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return 0;
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}
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static int ls2x_i2c_tx(struct ls2x_i2c_priv *priv, struct i2c_msg *msg)
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{
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int ret;
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u8 *buf = msg->buf;
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u16 len = msg->len;
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/* Contains steps to send start condition and address. */
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ret = ls2x_i2c_start(priv, msg);
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if (ret)
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return ret;
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while (len--) {
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writeb(*buf++, priv->base + I2C_LS2X_TXR);
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ret = ls2x_i2c_send_byte(priv, LS2X_CR_WRITE);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int ls2x_i2c_xfer_one(struct ls2x_i2c_priv *priv,
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struct i2c_msg *msg, bool stop)
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{
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int ret;
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if (msg->flags & I2C_M_RD)
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ret = ls2x_i2c_rx(priv, msg);
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else
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ret = ls2x_i2c_tx(priv, msg);
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if (ret < 0) {
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/* Fatel error. Needs reinit. */
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if (ret == -ETIMEDOUT)
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ls2x_i2c_init(priv);
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return ret;
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}
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if (stop) {
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/* Failed to issue STOP. Needs reinit. */
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ret = ls2x_i2c_stop(priv);
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if (ret)
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ls2x_i2c_init(priv);
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}
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return ret;
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}
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static int ls2x_i2c_master_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs, int num)
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{
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int ret;
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struct i2c_msg *msg, *emsg = msgs + num;
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struct ls2x_i2c_priv *priv = i2c_get_adapdata(adap);
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for (msg = msgs; msg < emsg; msg++) {
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ret = ls2x_i2c_xfer_one(priv, msg, msg == emsg - 1);
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if (ret)
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return ret;
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}
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return num;
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}
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static unsigned int ls2x_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm ls2x_i2c_algo = {
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.master_xfer = ls2x_i2c_master_xfer,
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.functionality = ls2x_i2c_func,
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};
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static int ls2x_i2c_probe(struct platform_device *pdev)
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{
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int ret, irq;
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struct i2c_adapter *adap;
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struct ls2x_i2c_priv *priv;
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struct device *dev = &pdev->dev;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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/* Map hardware registers */
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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/* Add the i2c adapter */
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adap = &priv->adapter;
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adap->retries = 5;
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adap->nr = pdev->id;
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adap->dev.parent = dev;
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adap->owner = THIS_MODULE;
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adap->algo = &ls2x_i2c_algo;
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adap->timeout = msecs_to_jiffies(100);
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device_set_node(&adap->dev, dev_fwnode(dev));
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i2c_set_adapdata(adap, priv);
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strscpy(adap->name, pdev->name, sizeof(adap->name));
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init_completion(&priv->cmd_complete);
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platform_set_drvdata(pdev, priv);
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ls2x_i2c_init(priv);
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ret = devm_request_irq(dev, irq, ls2x_i2c_isr, IRQF_SHARED, "ls2x-i2c",
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priv);
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if (ret < 0)
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return dev_err_probe(dev, ret, "Unable to request irq %d\n", irq);
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return devm_i2c_add_adapter(dev, adap);
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}
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static int ls2x_i2c_suspend(struct device *dev)
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{
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struct ls2x_i2c_priv *priv = dev_get_drvdata(dev);
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/* Disable interrupts */
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writeb(readb(priv->base + I2C_LS2X_CTR) & ~LS2X_CTR_IEN,
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priv->base + I2C_LS2X_CTR);
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return 0;
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}
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static int ls2x_i2c_resume(struct device *dev)
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{
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ls2x_i2c_init(dev_get_drvdata(dev));
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return 0;
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}
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static DEFINE_RUNTIME_DEV_PM_OPS(ls2x_i2c_pm_ops,
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ls2x_i2c_suspend, ls2x_i2c_resume, NULL);
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static const struct of_device_id ls2x_i2c_id_table[] = {
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{ .compatible = "loongson,ls2k-i2c" },
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{ .compatible = "loongson,ls7a-i2c" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, ls2x_i2c_id_table);
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static const struct acpi_device_id ls2x_i2c_acpi_match[] = {
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{ "LOON0004" }, /* Loongson LS7A */
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(acpi, ls2x_i2c_acpi_match);
|
||
|
|
|
||
|
|
static struct platform_driver ls2x_i2c_driver = {
|
||
|
|
.probe = ls2x_i2c_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "ls2x-i2c",
|
||
|
|
.pm = pm_sleep_ptr(&ls2x_i2c_pm_ops),
|
||
|
|
.of_match_table = ls2x_i2c_id_table,
|
||
|
|
.acpi_match_table = ls2x_i2c_acpi_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_platform_driver(ls2x_i2c_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Loongson LS2X I2C Bus driver");
|
||
|
|
MODULE_AUTHOR("Loongson Technology Corporation Limited");
|
||
|
|
MODULE_LICENSE("GPL");
|