52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/of_device.h>
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#include <linux/firmware/qcom/qcom_scm.h>
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#include <linux/ratelimit.h>
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#include "arm-smmu.h"
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#include "arm-smmu-qcom.h"
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void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
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{
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int ret;
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u32 tbu_pwr_status, sync_inv_ack, sync_inv_progress;
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struct qcom_smmu *qsmmu = container_of(smmu, struct qcom_smmu, smmu);
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const struct qcom_smmu_config *cfg;
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static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
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DEFAULT_RATELIMIT_BURST);
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if (__ratelimit(&rs)) {
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dev_err(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked\n");
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cfg = qsmmu->cfg;
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if (!cfg)
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return;
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ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_TBU_PWR_STATUS],
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&tbu_pwr_status);
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if (ret)
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dev_err(smmu->dev,
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"Failed to read TBU power status: %d\n", ret);
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ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK],
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&sync_inv_ack);
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if (ret)
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dev_err(smmu->dev,
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"Failed to read TBU sync/inv ack status: %d\n", ret);
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ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR],
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&sync_inv_progress);
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if (ret)
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dev_err(smmu->dev,
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"Failed to read TCU syn/inv progress: %d\n", ret);
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dev_err(smmu->dev,
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"TBU: power_status %#x sync_inv_ack %#x sync_inv_progress %#x\n",
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tbu_pwr_status, sync_inv_ack, sync_inv_progress);
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}
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}
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