501 lines
13 KiB
C
501 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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#define pr_fmt(fmt) "mvebu-sei: " fmt
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/msi.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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/* Cause register */
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#define GICP_SECR(idx) (0x0 + ((idx) * 0x4))
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/* Mask register */
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#define GICP_SEMR(idx) (0x20 + ((idx) * 0x4))
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#define GICP_SET_SEI_OFFSET 0x30
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#define SEI_IRQ_COUNT_PER_REG 32
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#define SEI_IRQ_REG_COUNT 2
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#define SEI_IRQ_COUNT (SEI_IRQ_COUNT_PER_REG * SEI_IRQ_REG_COUNT)
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#define SEI_IRQ_REG_IDX(irq_id) ((irq_id) / SEI_IRQ_COUNT_PER_REG)
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#define SEI_IRQ_REG_BIT(irq_id) ((irq_id) % SEI_IRQ_COUNT_PER_REG)
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struct mvebu_sei_interrupt_range {
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u32 first;
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u32 size;
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};
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struct mvebu_sei_caps {
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struct mvebu_sei_interrupt_range ap_range;
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struct mvebu_sei_interrupt_range cp_range;
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};
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struct mvebu_sei {
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struct device *dev;
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void __iomem *base;
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struct resource *res;
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struct irq_domain *sei_domain;
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struct irq_domain *ap_domain;
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struct irq_domain *cp_domain;
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const struct mvebu_sei_caps *caps;
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/* Lock on MSI allocations/releases */
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struct mutex cp_msi_lock;
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DECLARE_BITMAP(cp_msi_bitmap, SEI_IRQ_COUNT);
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/* Lock on IRQ masking register */
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raw_spinlock_t mask_lock;
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};
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static void mvebu_sei_ack_irq(struct irq_data *d)
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{
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struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
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u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq);
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writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)),
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sei->base + GICP_SECR(reg_idx));
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}
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static void mvebu_sei_mask_irq(struct irq_data *d)
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{
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struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
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u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq);
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unsigned long flags;
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/* 1 disables the interrupt */
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raw_spin_lock_irqsave(&sei->mask_lock, flags);
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reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx));
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reg |= BIT(SEI_IRQ_REG_BIT(d->hwirq));
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writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx));
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raw_spin_unlock_irqrestore(&sei->mask_lock, flags);
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}
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static void mvebu_sei_unmask_irq(struct irq_data *d)
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{
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struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
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u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq);
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unsigned long flags;
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/* 0 enables the interrupt */
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raw_spin_lock_irqsave(&sei->mask_lock, flags);
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reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx));
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reg &= ~BIT(SEI_IRQ_REG_BIT(d->hwirq));
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writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx));
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raw_spin_unlock_irqrestore(&sei->mask_lock, flags);
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}
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static int mvebu_sei_set_affinity(struct irq_data *d,
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const struct cpumask *mask_val,
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bool force)
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{
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return -EINVAL;
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}
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static int mvebu_sei_set_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which,
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bool state)
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{
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/* We can only clear the pending state by acking the interrupt */
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if (which != IRQCHIP_STATE_PENDING || state)
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return -EINVAL;
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mvebu_sei_ack_irq(d);
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return 0;
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}
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static struct irq_chip mvebu_sei_irq_chip = {
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.name = "SEI",
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.irq_ack = mvebu_sei_ack_irq,
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.irq_mask = mvebu_sei_mask_irq,
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.irq_unmask = mvebu_sei_unmask_irq,
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.irq_set_affinity = mvebu_sei_set_affinity,
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.irq_set_irqchip_state = mvebu_sei_set_irqchip_state,
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};
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static int mvebu_sei_ap_set_type(struct irq_data *data, unsigned int type)
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{
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if ((type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH)
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return -EINVAL;
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return 0;
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}
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static struct irq_chip mvebu_sei_ap_irq_chip = {
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.name = "AP SEI",
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.irq_ack = irq_chip_ack_parent,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_set_type = mvebu_sei_ap_set_type,
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};
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static void mvebu_sei_cp_compose_msi_msg(struct irq_data *data,
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struct msi_msg *msg)
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{
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struct mvebu_sei *sei = data->chip_data;
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phys_addr_t set = sei->res->start + GICP_SET_SEI_OFFSET;
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msg->data = data->hwirq + sei->caps->cp_range.first;
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msg->address_lo = lower_32_bits(set);
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msg->address_hi = upper_32_bits(set);
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}
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static int mvebu_sei_cp_set_type(struct irq_data *data, unsigned int type)
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{
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if ((type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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return 0;
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}
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static struct irq_chip mvebu_sei_cp_irq_chip = {
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.name = "CP SEI",
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.irq_ack = irq_chip_ack_parent,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_set_type = mvebu_sei_cp_set_type,
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.irq_compose_msi_msg = mvebu_sei_cp_compose_msi_msg,
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};
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static int mvebu_sei_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct mvebu_sei *sei = domain->host_data;
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struct irq_fwspec *fwspec = arg;
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/* Not much to do, just setup the irqdata */
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irq_domain_set_hwirq_and_chip(domain, virq, fwspec->param[0],
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&mvebu_sei_irq_chip, sei);
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return 0;
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}
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static void mvebu_sei_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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int i;
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for (i = 0; i < nr_irqs; i++) {
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struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
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irq_set_handler(virq + i, NULL);
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irq_domain_reset_irq_data(d);
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}
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}
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static const struct irq_domain_ops mvebu_sei_domain_ops = {
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.alloc = mvebu_sei_domain_alloc,
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.free = mvebu_sei_domain_free,
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};
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static int mvebu_sei_ap_translate(struct irq_domain *domain,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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*hwirq = fwspec->param[0];
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*type = IRQ_TYPE_LEVEL_HIGH;
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return 0;
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}
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static int mvebu_sei_ap_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct mvebu_sei *sei = domain->host_data;
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struct irq_fwspec fwspec;
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unsigned long hwirq;
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unsigned int type;
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int err;
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mvebu_sei_ap_translate(domain, arg, &hwirq, &type);
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fwspec.fwnode = domain->parent->fwnode;
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fwspec.param_count = 1;
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fwspec.param[0] = hwirq + sei->caps->ap_range.first;
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err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
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if (err)
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return err;
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irq_domain_set_info(domain, virq, hwirq,
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&mvebu_sei_ap_irq_chip, sei,
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handle_level_irq, NULL, NULL);
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irq_set_probe(virq);
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return 0;
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}
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static const struct irq_domain_ops mvebu_sei_ap_domain_ops = {
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.translate = mvebu_sei_ap_translate,
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.alloc = mvebu_sei_ap_alloc,
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.free = irq_domain_free_irqs_parent,
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};
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static void mvebu_sei_cp_release_irq(struct mvebu_sei *sei, unsigned long hwirq)
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{
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mutex_lock(&sei->cp_msi_lock);
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clear_bit(hwirq, sei->cp_msi_bitmap);
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mutex_unlock(&sei->cp_msi_lock);
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}
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static int mvebu_sei_cp_domain_alloc(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs,
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void *args)
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{
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struct mvebu_sei *sei = domain->host_data;
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struct irq_fwspec fwspec;
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unsigned long hwirq;
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int ret;
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/* The software only supports single allocations for now */
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if (nr_irqs != 1)
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return -ENOTSUPP;
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mutex_lock(&sei->cp_msi_lock);
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hwirq = find_first_zero_bit(sei->cp_msi_bitmap,
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sei->caps->cp_range.size);
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if (hwirq < sei->caps->cp_range.size)
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set_bit(hwirq, sei->cp_msi_bitmap);
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mutex_unlock(&sei->cp_msi_lock);
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if (hwirq == sei->caps->cp_range.size)
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return -ENOSPC;
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fwspec.fwnode = domain->parent->fwnode;
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fwspec.param_count = 1;
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fwspec.param[0] = hwirq + sei->caps->cp_range.first;
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ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
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if (ret)
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goto free_irq;
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irq_domain_set_info(domain, virq, hwirq,
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&mvebu_sei_cp_irq_chip, sei,
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handle_edge_irq, NULL, NULL);
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return 0;
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free_irq:
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mvebu_sei_cp_release_irq(sei, hwirq);
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return ret;
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}
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static void mvebu_sei_cp_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct mvebu_sei *sei = domain->host_data;
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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if (nr_irqs != 1 || d->hwirq >= sei->caps->cp_range.size) {
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dev_err(sei->dev, "Invalid hwirq %lu\n", d->hwirq);
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return;
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}
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mvebu_sei_cp_release_irq(sei, d->hwirq);
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irq_domain_free_irqs_parent(domain, virq, 1);
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}
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static const struct irq_domain_ops mvebu_sei_cp_domain_ops = {
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.alloc = mvebu_sei_cp_domain_alloc,
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.free = mvebu_sei_cp_domain_free,
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};
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static struct irq_chip mvebu_sei_msi_irq_chip = {
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.name = "SEI pMSI",
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.irq_ack = irq_chip_ack_parent,
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.irq_set_type = irq_chip_set_type_parent,
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};
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static struct msi_domain_ops mvebu_sei_msi_ops = {
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};
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static struct msi_domain_info mvebu_sei_msi_domain_info = {
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.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS,
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.ops = &mvebu_sei_msi_ops,
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.chip = &mvebu_sei_msi_irq_chip,
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};
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static void mvebu_sei_handle_cascade_irq(struct irq_desc *desc)
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{
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struct mvebu_sei *sei = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 idx;
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chained_irq_enter(chip, desc);
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for (idx = 0; idx < SEI_IRQ_REG_COUNT; idx++) {
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unsigned long irqmap;
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int bit;
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irqmap = readl_relaxed(sei->base + GICP_SECR(idx));
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for_each_set_bit(bit, &irqmap, SEI_IRQ_COUNT_PER_REG) {
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unsigned long hwirq;
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int err;
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hwirq = idx * SEI_IRQ_COUNT_PER_REG + bit;
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err = generic_handle_domain_irq(sei->sei_domain, hwirq);
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if (unlikely(err))
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dev_warn(sei->dev, "Spurious IRQ detected (hwirq %lu)\n", hwirq);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
chained_irq_exit(chip, desc);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void mvebu_sei_reset(struct mvebu_sei *sei)
|
||
|
|
{
|
||
|
|
u32 reg_idx;
|
||
|
|
|
||
|
|
/* Clear IRQ cause registers, mask all interrupts */
|
||
|
|
for (reg_idx = 0; reg_idx < SEI_IRQ_REG_COUNT; reg_idx++) {
|
||
|
|
writel_relaxed(0xFFFFFFFF, sei->base + GICP_SECR(reg_idx));
|
||
|
|
writel_relaxed(0xFFFFFFFF, sei->base + GICP_SEMR(reg_idx));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mvebu_sei_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct device_node *node = pdev->dev.of_node;
|
||
|
|
struct irq_domain *plat_domain;
|
||
|
|
struct mvebu_sei *sei;
|
||
|
|
u32 parent_irq;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
sei = devm_kzalloc(&pdev->dev, sizeof(*sei), GFP_KERNEL);
|
||
|
|
if (!sei)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
sei->dev = &pdev->dev;
|
||
|
|
|
||
|
|
mutex_init(&sei->cp_msi_lock);
|
||
|
|
raw_spin_lock_init(&sei->mask_lock);
|
||
|
|
|
||
|
|
sei->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||
|
|
sei->base = devm_ioremap_resource(sei->dev, sei->res);
|
||
|
|
if (IS_ERR(sei->base))
|
||
|
|
return PTR_ERR(sei->base);
|
||
|
|
|
||
|
|
/* Retrieve the SEI capabilities with the interrupt ranges */
|
||
|
|
sei->caps = of_device_get_match_data(&pdev->dev);
|
||
|
|
if (!sei->caps) {
|
||
|
|
dev_err(sei->dev,
|
||
|
|
"Could not retrieve controller capabilities\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Reserve the single (top-level) parent SPI IRQ from which all the
|
||
|
|
* interrupts handled by this driver will be signaled.
|
||
|
|
*/
|
||
|
|
parent_irq = irq_of_parse_and_map(node, 0);
|
||
|
|
if (parent_irq <= 0) {
|
||
|
|
dev_err(sei->dev, "Failed to retrieve top-level SPI IRQ\n");
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Create the root SEI domain */
|
||
|
|
sei->sei_domain = irq_domain_create_linear(of_node_to_fwnode(node),
|
||
|
|
(sei->caps->ap_range.size +
|
||
|
|
sei->caps->cp_range.size),
|
||
|
|
&mvebu_sei_domain_ops,
|
||
|
|
sei);
|
||
|
|
if (!sei->sei_domain) {
|
||
|
|
dev_err(sei->dev, "Failed to create SEI IRQ domain\n");
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto dispose_irq;
|
||
|
|
}
|
||
|
|
|
||
|
|
irq_domain_update_bus_token(sei->sei_domain, DOMAIN_BUS_NEXUS);
|
||
|
|
|
||
|
|
/* Create the 'wired' domain */
|
||
|
|
sei->ap_domain = irq_domain_create_hierarchy(sei->sei_domain, 0,
|
||
|
|
sei->caps->ap_range.size,
|
||
|
|
of_node_to_fwnode(node),
|
||
|
|
&mvebu_sei_ap_domain_ops,
|
||
|
|
sei);
|
||
|
|
if (!sei->ap_domain) {
|
||
|
|
dev_err(sei->dev, "Failed to create AP IRQ domain\n");
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto remove_sei_domain;
|
||
|
|
}
|
||
|
|
|
||
|
|
irq_domain_update_bus_token(sei->ap_domain, DOMAIN_BUS_WIRED);
|
||
|
|
|
||
|
|
/* Create the 'MSI' domain */
|
||
|
|
sei->cp_domain = irq_domain_create_hierarchy(sei->sei_domain, 0,
|
||
|
|
sei->caps->cp_range.size,
|
||
|
|
of_node_to_fwnode(node),
|
||
|
|
&mvebu_sei_cp_domain_ops,
|
||
|
|
sei);
|
||
|
|
if (!sei->cp_domain) {
|
||
|
|
pr_err("Failed to create CPs IRQ domain\n");
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto remove_ap_domain;
|
||
|
|
}
|
||
|
|
|
||
|
|
irq_domain_update_bus_token(sei->cp_domain, DOMAIN_BUS_GENERIC_MSI);
|
||
|
|
|
||
|
|
plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node),
|
||
|
|
&mvebu_sei_msi_domain_info,
|
||
|
|
sei->cp_domain);
|
||
|
|
if (!plat_domain) {
|
||
|
|
pr_err("Failed to create CPs MSI domain\n");
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto remove_cp_domain;
|
||
|
|
}
|
||
|
|
|
||
|
|
mvebu_sei_reset(sei);
|
||
|
|
|
||
|
|
irq_set_chained_handler_and_data(parent_irq,
|
||
|
|
mvebu_sei_handle_cascade_irq,
|
||
|
|
sei);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
remove_cp_domain:
|
||
|
|
irq_domain_remove(sei->cp_domain);
|
||
|
|
remove_ap_domain:
|
||
|
|
irq_domain_remove(sei->ap_domain);
|
||
|
|
remove_sei_domain:
|
||
|
|
irq_domain_remove(sei->sei_domain);
|
||
|
|
dispose_irq:
|
||
|
|
irq_dispose_mapping(parent_irq);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct mvebu_sei_caps mvebu_sei_ap806_caps = {
|
||
|
|
.ap_range = {
|
||
|
|
.first = 0,
|
||
|
|
.size = 21,
|
||
|
|
},
|
||
|
|
.cp_range = {
|
||
|
|
.first = 21,
|
||
|
|
.size = 43,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id mvebu_sei_of_match[] = {
|
||
|
|
{
|
||
|
|
.compatible = "marvell,ap806-sei",
|
||
|
|
.data = &mvebu_sei_ap806_caps,
|
||
|
|
},
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver mvebu_sei_driver = {
|
||
|
|
.probe = mvebu_sei_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "mvebu-sei",
|
||
|
|
.of_match_table = mvebu_sei_of_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
builtin_platform_driver(mvebu_sei_driver);
|