421 lines
9.1 KiB
C
421 lines
9.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Sony CXD2820R demodulator driver
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*
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* Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
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*/
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#include "cxd2820r_priv.h"
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int cxd2820r_set_frontend_t2(struct dvb_frontend *fe)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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struct i2c_client *client = priv->client[0];
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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int ret, bw_i;
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unsigned int utmp;
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u32 if_frequency;
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u8 buf[3], bw_param;
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u8 bw_params1[][5] = {
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{ 0x1c, 0xb3, 0x33, 0x33, 0x33 }, /* 5 MHz */
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{ 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
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{ 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
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{ 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
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};
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struct reg_val_mask tab[] = {
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{ 0x00080, 0x02, 0xff },
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{ 0x00081, 0x20, 0xff },
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{ 0x00085, 0x07, 0xff },
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{ 0x00088, 0x01, 0xff },
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{ 0x02069, 0x01, 0xff },
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{ 0x0207f, 0x2a, 0xff },
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{ 0x02082, 0x0a, 0xff },
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{ 0x02083, 0x0a, 0xff },
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{ 0x020cb, priv->if_agc_polarity << 6, 0x40 },
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{ 0x02070, priv->ts_mode, 0xff },
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{ 0x02071, !priv->ts_clk_inv << 6, 0x40 },
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{ 0x020b5, priv->spec_inv << 4, 0x10 },
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{ 0x02567, 0x07, 0x0f },
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{ 0x02569, 0x03, 0x03 },
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{ 0x02595, 0x1a, 0xff },
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{ 0x02596, 0x50, 0xff },
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{ 0x02a8c, 0x00, 0xff },
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{ 0x02a8d, 0x34, 0xff },
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{ 0x02a45, 0x06, 0x07 },
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{ 0x03f10, 0x0d, 0xff },
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{ 0x03f11, 0x02, 0xff },
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{ 0x03f12, 0x01, 0xff },
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{ 0x03f23, 0x2c, 0xff },
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{ 0x03f51, 0x13, 0xff },
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{ 0x03f52, 0x01, 0xff },
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{ 0x03f53, 0x00, 0xff },
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{ 0x027e6, 0x14, 0xff },
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{ 0x02786, 0x02, 0x07 },
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{ 0x02787, 0x40, 0xe0 },
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{ 0x027ef, 0x10, 0x18 },
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};
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dev_dbg(&client->dev,
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"delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d stream_id=%u\n",
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c->delivery_system, c->modulation, c->frequency,
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c->bandwidth_hz, c->inversion, c->stream_id);
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switch (c->bandwidth_hz) {
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case 5000000:
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bw_i = 0;
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bw_param = 3;
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break;
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case 6000000:
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bw_i = 1;
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bw_param = 2;
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break;
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case 7000000:
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bw_i = 2;
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bw_param = 1;
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break;
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case 8000000:
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bw_i = 3;
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bw_param = 0;
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break;
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default:
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return -EINVAL;
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}
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/* program tuner */
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if (fe->ops.tuner_ops.set_params)
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fe->ops.tuner_ops.set_params(fe);
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if (priv->delivery_system != SYS_DVBT2) {
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ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
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if (ret)
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goto error;
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}
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priv->delivery_system = SYS_DVBT2;
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/* program IF frequency */
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if (fe->ops.tuner_ops.get_if_frequency) {
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ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
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if (ret)
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goto error;
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dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
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} else {
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ret = -EINVAL;
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goto error;
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}
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utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
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buf[0] = (utmp >> 16) & 0xff;
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buf[1] = (utmp >> 8) & 0xff;
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buf[2] = (utmp >> 0) & 0xff;
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ret = regmap_bulk_write(priv->regmap[0], 0x20b6, buf, 3);
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if (ret)
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goto error;
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/* PLP filtering */
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if (c->stream_id > 255) {
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dev_dbg(&client->dev, "disable PLP filtering\n");
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ret = regmap_write(priv->regmap[0], 0x23ad, 0x00);
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if (ret)
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goto error;
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} else {
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dev_dbg(&client->dev, "enable PLP filtering\n");
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ret = regmap_write(priv->regmap[0], 0x23af, c->stream_id & 0xff);
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if (ret)
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goto error;
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ret = regmap_write(priv->regmap[0], 0x23ad, 0x01);
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if (ret)
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goto error;
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}
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ret = regmap_bulk_write(priv->regmap[0], 0x209f, bw_params1[bw_i], 5);
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if (ret)
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goto error;
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ret = regmap_update_bits(priv->regmap[0], 0x20d7, 0xc0, bw_param << 6);
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if (ret)
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goto error;
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ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
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if (ret)
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goto error;
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ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
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if (ret)
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goto error;
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return ret;
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error:
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dev_dbg(&client->dev, "failed=%d\n", ret);
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return ret;
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}
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int cxd2820r_get_frontend_t2(struct dvb_frontend *fe,
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struct dtv_frontend_properties *c)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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struct i2c_client *client = priv->client[0];
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int ret;
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unsigned int utmp;
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u8 buf[2];
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dev_dbg(&client->dev, "\n");
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ret = regmap_bulk_read(priv->regmap[0], 0x205c, buf, 2);
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if (ret)
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goto error;
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switch ((buf[0] >> 0) & 0x07) {
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case 0:
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c->transmission_mode = TRANSMISSION_MODE_2K;
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break;
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case 1:
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c->transmission_mode = TRANSMISSION_MODE_8K;
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break;
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case 2:
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c->transmission_mode = TRANSMISSION_MODE_4K;
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break;
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case 3:
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c->transmission_mode = TRANSMISSION_MODE_1K;
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break;
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case 4:
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c->transmission_mode = TRANSMISSION_MODE_16K;
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break;
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case 5:
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c->transmission_mode = TRANSMISSION_MODE_32K;
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break;
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}
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switch ((buf[1] >> 4) & 0x07) {
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case 0:
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c->guard_interval = GUARD_INTERVAL_1_32;
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break;
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case 1:
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c->guard_interval = GUARD_INTERVAL_1_16;
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break;
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case 2:
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c->guard_interval = GUARD_INTERVAL_1_8;
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break;
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case 3:
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c->guard_interval = GUARD_INTERVAL_1_4;
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break;
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case 4:
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c->guard_interval = GUARD_INTERVAL_1_128;
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break;
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case 5:
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c->guard_interval = GUARD_INTERVAL_19_128;
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break;
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case 6:
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c->guard_interval = GUARD_INTERVAL_19_256;
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break;
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}
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ret = regmap_bulk_read(priv->regmap[0], 0x225b, buf, 2);
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if (ret)
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goto error;
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switch ((buf[0] >> 0) & 0x07) {
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case 0:
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c->fec_inner = FEC_1_2;
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break;
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case 1:
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c->fec_inner = FEC_3_5;
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break;
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case 2:
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c->fec_inner = FEC_2_3;
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break;
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case 3:
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c->fec_inner = FEC_3_4;
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break;
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case 4:
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c->fec_inner = FEC_4_5;
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break;
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case 5:
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c->fec_inner = FEC_5_6;
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break;
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}
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switch ((buf[1] >> 0) & 0x07) {
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case 0:
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c->modulation = QPSK;
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break;
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case 1:
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c->modulation = QAM_16;
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break;
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case 2:
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c->modulation = QAM_64;
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break;
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case 3:
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c->modulation = QAM_256;
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break;
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}
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ret = regmap_read(priv->regmap[0], 0x20b5, &utmp);
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if (ret)
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goto error;
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switch ((utmp >> 4) & 0x01) {
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case 0:
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c->inversion = INVERSION_OFF;
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break;
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case 1:
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c->inversion = INVERSION_ON;
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break;
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}
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return ret;
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error:
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dev_dbg(&client->dev, "failed=%d\n", ret);
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return ret;
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}
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int cxd2820r_read_status_t2(struct dvb_frontend *fe, enum fe_status *status)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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struct i2c_client *client = priv->client[0];
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int ret;
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unsigned int utmp, utmp1, utmp2;
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u8 buf[4];
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/* Lock detection */
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ret = regmap_bulk_read(priv->regmap[0], 0x2010, &buf[0], 1);
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if (ret)
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goto error;
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utmp1 = (buf[0] >> 0) & 0x07;
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utmp2 = (buf[0] >> 5) & 0x01;
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if (utmp1 == 6 && utmp2 == 1) {
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*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
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FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
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} else if (utmp1 == 6 || utmp2 == 1) {
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*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
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FE_HAS_VITERBI | FE_HAS_SYNC;
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} else {
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*status = 0;
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}
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dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
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*status, 1, buf, utmp1, utmp2);
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/* Signal strength */
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if (*status & FE_HAS_SIGNAL) {
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unsigned int strength;
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ret = regmap_bulk_read(priv->regmap[0], 0x2026, buf, 2);
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if (ret)
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goto error;
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utmp = buf[0] << 8 | buf[1] << 0;
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utmp = ~utmp & 0x0fff;
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/* Scale value to 0x0000-0xffff */
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strength = utmp << 4 | utmp >> 8;
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c->strength.len = 1;
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c->strength.stat[0].scale = FE_SCALE_RELATIVE;
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c->strength.stat[0].uvalue = strength;
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} else {
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c->strength.len = 1;
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c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
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}
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/* CNR */
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if (*status & FE_HAS_VITERBI) {
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unsigned int cnr;
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ret = regmap_bulk_read(priv->regmap[0], 0x2028, buf, 2);
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if (ret)
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goto error;
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utmp = buf[0] << 8 | buf[1] << 0;
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utmp = utmp & 0x0fff;
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#define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
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if (utmp)
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cnr = div_u64((u64)(intlog10(utmp)
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- CXD2820R_LOG10_8_24) * 10000,
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(1 << 24));
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else
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cnr = 0;
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c->cnr.len = 1;
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c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
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c->cnr.stat[0].svalue = cnr;
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} else {
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c->cnr.len = 1;
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c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
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}
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/* BER */
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if (*status & FE_HAS_SYNC) {
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unsigned int post_bit_error;
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ret = regmap_bulk_read(priv->regmap[0], 0x2039, buf, 4);
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if (ret)
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goto error;
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if ((buf[0] >> 4) & 0x01) {
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post_bit_error = buf[0] << 24 | buf[1] << 16 |
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buf[2] << 8 | buf[3] << 0;
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post_bit_error &= 0x0fffffff;
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||
|
|
} else {
|
||
|
|
post_bit_error = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
priv->post_bit_error += post_bit_error;
|
||
|
|
|
||
|
|
c->post_bit_error.len = 1;
|
||
|
|
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
|
||
|
|
c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
|
||
|
|
} else {
|
||
|
|
c->post_bit_error.len = 1;
|
||
|
|
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
error:
|
||
|
|
dev_dbg(&client->dev, "failed=%d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int cxd2820r_sleep_t2(struct dvb_frontend *fe)
|
||
|
|
{
|
||
|
|
struct cxd2820r_priv *priv = fe->demodulator_priv;
|
||
|
|
struct i2c_client *client = priv->client[0];
|
||
|
|
int ret;
|
||
|
|
static const struct reg_val_mask tab[] = {
|
||
|
|
{ 0x000ff, 0x1f, 0xff },
|
||
|
|
{ 0x00085, 0x00, 0xff },
|
||
|
|
{ 0x00088, 0x01, 0xff },
|
||
|
|
{ 0x02069, 0x00, 0xff },
|
||
|
|
{ 0x00081, 0x00, 0xff },
|
||
|
|
{ 0x00080, 0x00, 0xff },
|
||
|
|
};
|
||
|
|
|
||
|
|
dev_dbg(&client->dev, "\n");
|
||
|
|
|
||
|
|
ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
|
||
|
|
if (ret)
|
||
|
|
goto error;
|
||
|
|
|
||
|
|
priv->delivery_system = SYS_UNDEFINED;
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
error:
|
||
|
|
dev_dbg(&client->dev, "failed=%d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe,
|
||
|
|
struct dvb_frontend_tune_settings *s)
|
||
|
|
{
|
||
|
|
s->min_delay_ms = 1500;
|
||
|
|
s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
|
||
|
|
s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|