155 lines
4.0 KiB
C
155 lines
4.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Driver for Renesas RZ/G2L CRU
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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#ifndef __RZG2L_CRU__
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#define __RZG2L_CRU__
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#include <linux/reset.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-dev.h>
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#include <media/v4l2-device.h>
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#include <media/videobuf2-v4l2.h>
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/* Number of HW buffers */
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#define RZG2L_CRU_HW_BUFFER_MAX 8
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#define RZG2L_CRU_HW_BUFFER_DEFAULT 3
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/* Address alignment mask for HW buffers */
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#define RZG2L_CRU_HW_BUFFER_MASK 0x1ff
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/* Maximum number of CSI2 virtual channels */
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#define RZG2L_CRU_CSI2_VCHANNEL 4
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#define RZG2L_CRU_MIN_INPUT_WIDTH 320
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#define RZG2L_CRU_MAX_INPUT_WIDTH 2800
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#define RZG2L_CRU_MIN_INPUT_HEIGHT 240
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#define RZG2L_CRU_MAX_INPUT_HEIGHT 4095
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/**
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* enum rzg2l_cru_dma_state - DMA states
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* @RZG2L_CRU_DMA_STOPPED: No operation in progress
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* @RZG2L_CRU_DMA_STARTING: Capture starting up
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* @RZG2L_CRU_DMA_RUNNING: Operation in progress have buffers
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* @RZG2L_CRU_DMA_STOPPING: Stopping operation
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*/
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enum rzg2l_cru_dma_state {
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RZG2L_CRU_DMA_STOPPED = 0,
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RZG2L_CRU_DMA_STARTING,
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RZG2L_CRU_DMA_RUNNING,
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RZG2L_CRU_DMA_STOPPING,
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};
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struct rzg2l_cru_csi {
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struct v4l2_async_subdev *asd;
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struct v4l2_subdev *subdev;
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u32 channel;
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};
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struct rzg2l_cru_ip {
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struct v4l2_subdev subdev;
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struct media_pad pads[2];
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struct v4l2_async_notifier notifier;
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struct v4l2_subdev *remote;
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};
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/**
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* struct rzg2l_cru_dev - Renesas CRU device structure
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* @dev: (OF) device
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* @base: device I/O register space remapped to virtual memory
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* @info: info about CRU instance
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*
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* @presetn: CRU_PRESETN reset line
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* @aresetn: CRU_ARESETN reset line
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*
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* @vclk: CRU Main clock
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*
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* @image_conv_irq: Holds image conversion interrupt number
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*
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* @vdev: V4L2 video device associated with CRU
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* @v4l2_dev: V4L2 device
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* @num_buf: Holds the current number of buffers enabled
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* @notifier: V4L2 asynchronous subdevs notifier
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*
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* @ip: Image processing subdev info
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* @csi: CSI info
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* @mdev: media device
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* @mdev_lock: protects the count, notifier and csi members
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* @pad: media pad for the video device entity
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*
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* @lock: protects @queue
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* @queue: vb2 buffers queue
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* @scratch: cpu address for scratch buffer
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* @scratch_phys: physical address of the scratch buffer
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*
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* @qlock: protects @queue_buf, @buf_list, @sequence
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* @state
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* @queue_buf: Keeps track of buffers given to HW slot
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* @buf_list: list of queued buffers
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* @sequence: V4L2 buffers sequence number
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* @state: keeps track of operation state
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*
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* @format: active V4L2 pixel format
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*/
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struct rzg2l_cru_dev {
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struct device *dev;
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void __iomem *base;
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const struct rzg2l_cru_info *info;
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struct reset_control *presetn;
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struct reset_control *aresetn;
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struct clk *vclk;
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int image_conv_irq;
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struct video_device vdev;
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struct v4l2_device v4l2_dev;
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u8 num_buf;
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struct v4l2_async_notifier notifier;
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struct rzg2l_cru_ip ip;
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struct rzg2l_cru_csi csi;
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struct media_device mdev;
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struct mutex mdev_lock;
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struct media_pad pad;
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struct mutex lock;
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struct vb2_queue queue;
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void *scratch;
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dma_addr_t scratch_phys;
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spinlock_t qlock;
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struct vb2_v4l2_buffer *queue_buf[RZG2L_CRU_HW_BUFFER_MAX];
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struct list_head buf_list;
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unsigned int sequence;
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enum rzg2l_cru_dma_state state;
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struct v4l2_pix_format format;
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};
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void rzg2l_cru_vclk_unprepare(struct rzg2l_cru_dev *cru);
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int rzg2l_cru_vclk_prepare(struct rzg2l_cru_dev *cru);
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int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru);
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void rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev *cru);
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int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru);
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void rzg2l_cru_dma_unregister(struct rzg2l_cru_dev *cru);
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int rzg2l_cru_video_register(struct rzg2l_cru_dev *cru);
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void rzg2l_cru_video_unregister(struct rzg2l_cru_dev *cru);
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const struct v4l2_format_info *rzg2l_cru_format_from_pixel(u32 format);
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int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev *cru);
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void rzg2l_cru_ip_subdev_unregister(struct rzg2l_cru_dev *cru);
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struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru);
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#endif
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