285 lines
8.1 KiB
C
285 lines
8.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Hantro G1 post-processor support
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*
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* Copyright (C) 2019 Collabora, Ltd.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/types.h>
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#include "hantro.h"
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#include "hantro_hw.h"
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#include "hantro_g1_regs.h"
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#include "hantro_g2_regs.h"
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#include "hantro_v4l2.h"
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#define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \
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{ \
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hantro_reg_write(vpu, \
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&hantro_g1_postproc_regs.reg_name, \
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val); \
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}
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#define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \
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{ \
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hantro_reg_write_s(vpu, \
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&hantro_g1_postproc_regs.reg_name, \
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val); \
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}
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#define VPU_PP_IN_YUYV 0x0
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#define VPU_PP_IN_NV12 0x1
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#define VPU_PP_IN_YUV420 0x2
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#define VPU_PP_IN_YUV240_TILED 0x5
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#define VPU_PP_OUT_RGB 0x0
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#define VPU_PP_OUT_YUYV 0x3
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static const struct hantro_postproc_regs hantro_g1_postproc_regs = {
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.pipeline_en = {G1_REG_PP_INTERRUPT, 1, 0x1},
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.max_burst = {G1_REG_PP_DEV_CONFIG, 0, 0x1f},
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.clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1},
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.out_swap32 = {G1_REG_PP_DEV_CONFIG, 5, 0x1},
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.out_endian = {G1_REG_PP_DEV_CONFIG, 6, 0x1},
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.out_luma_base = {G1_REG_PP_OUT_LUMA_BASE, 0, 0xffffffff},
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.input_width = {G1_REG_PP_INPUT_SIZE, 0, 0x1ff},
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.input_height = {G1_REG_PP_INPUT_SIZE, 9, 0x1ff},
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.output_width = {G1_REG_PP_CONTROL, 4, 0x7ff},
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.output_height = {G1_REG_PP_CONTROL, 15, 0x7ff},
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.input_fmt = {G1_REG_PP_CONTROL, 29, 0x7},
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.output_fmt = {G1_REG_PP_CONTROL, 26, 0x7},
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.orig_width = {G1_REG_PP_MASK1_ORIG_WIDTH, 23, 0x1ff},
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.display_width = {G1_REG_PP_DISPLAY_WIDTH, 0, 0xfff},
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};
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bool hantro_needs_postproc(const struct hantro_ctx *ctx,
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const struct hantro_fmt *fmt)
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{
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if (ctx->is_encoder)
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return false;
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return fmt->postprocessed;
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}
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static void hantro_postproc_g1_enable(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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struct vb2_v4l2_buffer *dst_buf;
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u32 src_pp_fmt, dst_pp_fmt;
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dma_addr_t dst_dma;
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/* Turn on pipeline mode. Must be done first. */
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HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1);
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src_pp_fmt = VPU_PP_IN_NV12;
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switch (ctx->vpu_dst_fmt->fourcc) {
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case V4L2_PIX_FMT_YUYV:
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dst_pp_fmt = VPU_PP_OUT_YUYV;
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break;
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default:
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WARN(1, "output format %d not supported by the post-processor, this wasn't expected.",
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ctx->vpu_dst_fmt->fourcc);
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dst_pp_fmt = 0;
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break;
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}
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dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
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dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
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HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1);
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HANTRO_PP_REG_WRITE(vpu, out_endian, 0x1);
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HANTRO_PP_REG_WRITE(vpu, out_swap32, 0x1);
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HANTRO_PP_REG_WRITE(vpu, max_burst, 16);
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HANTRO_PP_REG_WRITE(vpu, out_luma_base, dst_dma);
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HANTRO_PP_REG_WRITE(vpu, input_width, MB_WIDTH(ctx->dst_fmt.width));
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HANTRO_PP_REG_WRITE(vpu, input_height, MB_HEIGHT(ctx->dst_fmt.height));
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HANTRO_PP_REG_WRITE(vpu, input_fmt, src_pp_fmt);
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HANTRO_PP_REG_WRITE(vpu, output_fmt, dst_pp_fmt);
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HANTRO_PP_REG_WRITE(vpu, output_width, ctx->dst_fmt.width);
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HANTRO_PP_REG_WRITE(vpu, output_height, ctx->dst_fmt.height);
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HANTRO_PP_REG_WRITE(vpu, orig_width, MB_WIDTH(ctx->dst_fmt.width));
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HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width);
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}
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static int down_scale_factor(struct hantro_ctx *ctx)
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{
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if (ctx->src_fmt.width == ctx->dst_fmt.width)
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return 0;
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return DIV_ROUND_CLOSEST(ctx->src_fmt.width, ctx->dst_fmt.width);
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}
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static void hantro_postproc_g2_enable(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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struct vb2_v4l2_buffer *dst_buf;
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int down_scale = down_scale_factor(ctx);
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int out_depth;
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size_t chroma_offset;
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dma_addr_t dst_dma;
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dst_buf = hantro_get_dst_buf(ctx);
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dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
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chroma_offset = ctx->dst_fmt.plane_fmt[0].bytesperline *
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ctx->dst_fmt.height;
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if (down_scale) {
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hantro_reg_write(vpu, &g2_down_scale_e, 1);
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hantro_reg_write(vpu, &g2_down_scale_y, down_scale >> 2);
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hantro_reg_write(vpu, &g2_down_scale_x, down_scale >> 2);
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hantro_write_addr(vpu, G2_DS_DST, dst_dma);
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hantro_write_addr(vpu, G2_DS_DST_CHR, dst_dma + (chroma_offset >> down_scale));
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} else {
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hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma);
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hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset);
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}
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out_depth = hantro_get_format_depth(ctx->dst_fmt.pixelformat);
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if (ctx->dev->variant->legacy_regs) {
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u8 pp_shift = 0;
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if (out_depth > 8)
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pp_shift = 16 - out_depth;
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hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, out_depth);
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hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift);
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} else {
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hantro_reg_write(vpu, &g2_output_8_bits, out_depth > 8 ? 0 : 1);
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hantro_reg_write(vpu, &g2_output_format, out_depth > 8 ? 1 : 0);
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}
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hantro_reg_write(vpu, &g2_out_rs_e, 1);
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}
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static int hantro_postproc_g2_enum_framesizes(struct hantro_ctx *ctx,
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struct v4l2_frmsizeenum *fsize)
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{
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/**
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* G2 scaler can scale down by 0, 2, 4 or 8
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* use fsize->index has power of 2 diviser
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**/
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if (fsize->index > 3)
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return -EINVAL;
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if (!ctx->src_fmt.width || !ctx->src_fmt.height)
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return -EINVAL;
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fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
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fsize->discrete.width = ctx->src_fmt.width >> fsize->index;
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fsize->discrete.height = ctx->src_fmt.height >> fsize->index;
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return 0;
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}
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void hantro_postproc_free(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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unsigned int i;
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for (i = 0; i < VB2_MAX_FRAME; ++i) {
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struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i];
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if (priv->cpu) {
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dma_free_attrs(vpu->dev, priv->size, priv->cpu,
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priv->dma, priv->attrs);
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priv->cpu = NULL;
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}
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}
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}
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int hantro_postproc_alloc(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
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struct vb2_queue *cap_queue = &m2m_ctx->cap_q_ctx.q;
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unsigned int num_buffers = cap_queue->num_buffers;
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struct v4l2_pix_format_mplane pix_mp;
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const struct hantro_fmt *fmt;
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unsigned int i, buf_size;
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/* this should always pick native format */
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fmt = hantro_get_default_fmt(ctx, false);
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if (!fmt)
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return -EINVAL;
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v4l2_fill_pixfmt_mp(&pix_mp, fmt->fourcc, ctx->src_fmt.width,
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ctx->src_fmt.height);
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buf_size = pix_mp.plane_fmt[0].sizeimage;
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if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE)
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buf_size += hantro_h264_mv_size(pix_mp.width,
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pix_mp.height);
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else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME)
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buf_size += hantro_vp9_mv_size(pix_mp.width,
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pix_mp.height);
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else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE)
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buf_size += hantro_hevc_mv_size(pix_mp.width,
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pix_mp.height);
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for (i = 0; i < num_buffers; ++i) {
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struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i];
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/*
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* The buffers on this queue are meant as intermediate
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* buffers for the decoder, so no mapping is needed.
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*/
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priv->attrs = DMA_ATTR_NO_KERNEL_MAPPING;
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priv->cpu = dma_alloc_attrs(vpu->dev, buf_size, &priv->dma,
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GFP_KERNEL, priv->attrs);
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if (!priv->cpu)
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return -ENOMEM;
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priv->size = buf_size;
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}
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return 0;
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}
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static void hantro_postproc_g1_disable(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0);
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}
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static void hantro_postproc_g2_disable(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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hantro_reg_write(vpu, &g2_out_rs_e, 0);
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}
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void hantro_postproc_disable(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->disable)
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vpu->variant->postproc_ops->disable(ctx);
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}
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void hantro_postproc_enable(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enable)
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vpu->variant->postproc_ops->enable(ctx);
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}
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int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx,
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struct v4l2_frmsizeenum *fsize)
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{
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struct hantro_dev *vpu = ctx->dev;
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if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enum_framesizes)
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return vpu->variant->postproc_ops->enum_framesizes(ctx, fsize);
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return -EINVAL;
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}
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const struct hantro_postproc_ops hantro_g1_postproc_ops = {
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.enable = hantro_postproc_g1_enable,
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.disable = hantro_postproc_g1_disable,
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};
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const struct hantro_postproc_ops hantro_g2_postproc_ops = {
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.enable = hantro_postproc_g2_enable,
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.disable = hantro_postproc_g2_disable,
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.enum_framesizes = hantro_postproc_g2_enum_framesizes,
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};
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