401 lines
9.8 KiB
C
401 lines
9.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Hantro VPU codec driver
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*
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* Copyright (C) 2019 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include "hantro.h"
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#include "hantro_jpeg.h"
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#include "hantro_g1_regs.h"
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#include "hantro_g2_regs.h"
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#define CTRL_SOFT_RESET 0x00
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#define RESET_G1 BIT(1)
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#define RESET_G2 BIT(0)
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#define CTRL_CLOCK_ENABLE 0x04
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#define CLOCK_G1 BIT(1)
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#define CLOCK_G2 BIT(0)
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#define CTRL_G1_DEC_FUSE 0x08
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#define CTRL_G1_PP_FUSE 0x0c
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#define CTRL_G2_DEC_FUSE 0x10
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static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits)
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{
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u32 val;
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/* Assert */
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val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);
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val &= ~reset_bits;
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writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);
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udelay(2);
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/* Release */
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val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);
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val |= reset_bits;
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writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);
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}
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static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits)
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{
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u32 val;
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val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE);
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val |= clock_bits;
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writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE);
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}
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static int imx8mq_runtime_resume(struct hantro_dev *vpu)
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{
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int ret;
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ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks);
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if (ret) {
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dev_err(vpu->dev, "Failed to enable clocks\n");
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return ret;
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}
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imx8m_soft_reset(vpu, RESET_G1 | RESET_G2);
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imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2);
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/* Set values of the fuse registers */
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writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE);
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writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE);
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writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE);
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clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks);
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return 0;
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}
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/*
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* Supported formats.
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*/
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static const struct hantro_fmt imx8m_vpu_postproc_fmts[] = {
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{
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.fourcc = V4L2_PIX_FMT_YUYV,
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.codec_mode = HANTRO_MODE_NONE,
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.postprocessed = true,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = MB_DIM,
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},
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},
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};
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static const struct hantro_fmt imx8m_vpu_dec_fmts[] = {
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{
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.fourcc = V4L2_PIX_FMT_NV12,
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.codec_mode = HANTRO_MODE_NONE,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
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.codec_mode = HANTRO_MODE_MPEG2_DEC,
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.max_depth = 2,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_FHD_WIDTH,
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.step_width = MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_FHD_HEIGHT,
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.step_height = MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_VP8_FRAME,
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.codec_mode = HANTRO_MODE_VP8_DEC,
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.max_depth = 2,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_H264_SLICE,
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.codec_mode = HANTRO_MODE_H264_DEC,
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.max_depth = 2,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = MB_DIM,
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},
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},
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};
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static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = {
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{
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.fourcc = V4L2_PIX_FMT_NV12,
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.codec_mode = HANTRO_MODE_NONE,
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.postprocessed = true,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_P010,
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.codec_mode = HANTRO_MODE_NONE,
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.postprocessed = true,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = MB_DIM,
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},
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},
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};
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static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
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{
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.fourcc = V4L2_PIX_FMT_NV12_4L4,
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.codec_mode = HANTRO_MODE_NONE,
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.match_depth = true,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = TILE_MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = TILE_MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_P010_4L4,
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.codec_mode = HANTRO_MODE_NONE,
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.match_depth = true,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = TILE_MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = TILE_MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_HEVC_SLICE,
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.codec_mode = HANTRO_MODE_HEVC_DEC,
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.max_depth = 2,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = TILE_MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = TILE_MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_VP9_FRAME,
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.codec_mode = HANTRO_MODE_VP9_DEC,
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.max_depth = 2,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = TILE_MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = TILE_MB_DIM,
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},
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},
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};
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static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)
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{
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struct hantro_dev *vpu = dev_id;
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enum vb2_buffer_state state;
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u32 status;
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status = vdpu_read(vpu, G1_REG_INTERRUPT);
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state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ?
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VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
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vdpu_write(vpu, 0, G1_REG_INTERRUPT);
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vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
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hantro_irq_done(vpu, state);
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return IRQ_HANDLED;
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}
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static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)
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{
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vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1];
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return 0;
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}
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static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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imx8m_soft_reset(vpu, RESET_G1);
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}
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/*
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* Supported codec ops.
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*/
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static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = {
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[HANTRO_MODE_MPEG2_DEC] = {
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.run = hantro_g1_mpeg2_dec_run,
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.reset = imx8m_vpu_g1_reset,
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.init = hantro_mpeg2_dec_init,
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.exit = hantro_mpeg2_dec_exit,
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},
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[HANTRO_MODE_VP8_DEC] = {
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.run = hantro_g1_vp8_dec_run,
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.reset = imx8m_vpu_g1_reset,
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.init = hantro_vp8_dec_init,
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.exit = hantro_vp8_dec_exit,
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},
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[HANTRO_MODE_H264_DEC] = {
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.run = hantro_g1_h264_dec_run,
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.reset = imx8m_vpu_g1_reset,
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.init = hantro_h264_dec_init,
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.exit = hantro_h264_dec_exit,
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},
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};
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static const struct hantro_codec_ops imx8mq_vpu_g1_codec_ops[] = {
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[HANTRO_MODE_MPEG2_DEC] = {
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.run = hantro_g1_mpeg2_dec_run,
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.init = hantro_mpeg2_dec_init,
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.exit = hantro_mpeg2_dec_exit,
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},
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[HANTRO_MODE_VP8_DEC] = {
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.run = hantro_g1_vp8_dec_run,
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.init = hantro_vp8_dec_init,
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.exit = hantro_vp8_dec_exit,
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},
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[HANTRO_MODE_H264_DEC] = {
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.run = hantro_g1_h264_dec_run,
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.init = hantro_h264_dec_init,
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.exit = hantro_h264_dec_exit,
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},
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};
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static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = {
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[HANTRO_MODE_HEVC_DEC] = {
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.run = hantro_g2_hevc_dec_run,
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.init = hantro_hevc_dec_init,
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.exit = hantro_hevc_dec_exit,
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},
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[HANTRO_MODE_VP9_DEC] = {
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.run = hantro_g2_vp9_dec_run,
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.done = hantro_g2_vp9_dec_done,
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.init = hantro_vp9_dec_init,
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.exit = hantro_vp9_dec_exit,
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},
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};
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/*
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* VPU variants.
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*/
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static const struct hantro_irq imx8mq_irqs[] = {
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{ "g1", imx8m_vpu_g1_irq },
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};
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static const struct hantro_irq imx8mq_g2_irqs[] = {
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{ "g2", hantro_g2_irq },
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};
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static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" };
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static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" };
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static const char * const imx8mq_g1_clk_names[] = { "g1" };
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static const char * const imx8mq_g2_clk_names[] = { "g2" };
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const struct hantro_variant imx8mq_vpu_variant = {
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.dec_fmts = imx8m_vpu_dec_fmts,
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.num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts),
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.postproc_fmts = imx8m_vpu_postproc_fmts,
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.num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts),
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|
.postproc_ops = &hantro_g1_postproc_ops,
|
||
|
|
.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
|
||
|
|
HANTRO_H264_DECODER,
|
||
|
|
.codec_ops = imx8mq_vpu_codec_ops,
|
||
|
|
.init = imx8mq_vpu_hw_init,
|
||
|
|
.runtime_resume = imx8mq_runtime_resume,
|
||
|
|
.irqs = imx8mq_irqs,
|
||
|
|
.num_irqs = ARRAY_SIZE(imx8mq_irqs),
|
||
|
|
.clk_names = imx8mq_clk_names,
|
||
|
|
.num_clocks = ARRAY_SIZE(imx8mq_clk_names),
|
||
|
|
.reg_names = imx8mq_reg_names,
|
||
|
|
.num_regs = ARRAY_SIZE(imx8mq_reg_names)
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct hantro_variant imx8mq_vpu_g1_variant = {
|
||
|
|
.dec_fmts = imx8m_vpu_dec_fmts,
|
||
|
|
.num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts),
|
||
|
|
.postproc_fmts = imx8m_vpu_postproc_fmts,
|
||
|
|
.num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts),
|
||
|
|
.postproc_ops = &hantro_g1_postproc_ops,
|
||
|
|
.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
|
||
|
|
HANTRO_H264_DECODER,
|
||
|
|
.codec_ops = imx8mq_vpu_g1_codec_ops,
|
||
|
|
.irqs = imx8mq_irqs,
|
||
|
|
.num_irqs = ARRAY_SIZE(imx8mq_irqs),
|
||
|
|
.clk_names = imx8mq_g1_clk_names,
|
||
|
|
.num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names),
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct hantro_variant imx8mq_vpu_g2_variant = {
|
||
|
|
.dec_offset = 0x0,
|
||
|
|
.dec_fmts = imx8m_vpu_g2_dec_fmts,
|
||
|
|
.num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts),
|
||
|
|
.postproc_fmts = imx8m_vpu_g2_postproc_fmts,
|
||
|
|
.num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_g2_postproc_fmts),
|
||
|
|
.postproc_ops = &hantro_g2_postproc_ops,
|
||
|
|
.codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER,
|
||
|
|
.codec_ops = imx8mq_vpu_g2_codec_ops,
|
||
|
|
.irqs = imx8mq_g2_irqs,
|
||
|
|
.num_irqs = ARRAY_SIZE(imx8mq_g2_irqs),
|
||
|
|
.clk_names = imx8mq_g2_clk_names,
|
||
|
|
.num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names),
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct hantro_variant imx8mm_vpu_g1_variant = {
|
||
|
|
.dec_fmts = imx8m_vpu_dec_fmts,
|
||
|
|
.num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts),
|
||
|
|
.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
|
||
|
|
HANTRO_H264_DECODER,
|
||
|
|
.codec_ops = imx8mq_vpu_g1_codec_ops,
|
||
|
|
.irqs = imx8mq_irqs,
|
||
|
|
.num_irqs = ARRAY_SIZE(imx8mq_irqs),
|
||
|
|
.clk_names = imx8mq_g1_clk_names,
|
||
|
|
.num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names),
|
||
|
|
};
|