349 lines
9.0 KiB
C
349 lines
9.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
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* Vincent Yang <vincent.yang@tw.fujitsu.com>
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* Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org>
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* Copyright (C) 2019 Socionext Inc.
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* Takao Orito <orito.takao@socionext.com>
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*/
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/gpio/consumer.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/property.h>
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#include "sdhci-pltfm.h"
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#include "sdhci_f_sdh30.h"
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/* milbeaut bridge controller register */
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#define MLB_SOFT_RESET 0x0200
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#define MLB_SOFT_RESET_RSTX BIT(0)
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#define MLB_WP_CD_LED_SET 0x0210
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#define MLB_WP_CD_LED_SET_LED_INV BIT(2)
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#define MLB_CR_SET 0x0220
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#define MLB_CR_SET_CR_TOCLKUNIT BIT(24)
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#define MLB_CR_SET_CR_TOCLKFREQ_SFT (16)
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#define MLB_CR_SET_CR_TOCLKFREQ_MASK (0x3F << MLB_CR_SET_CR_TOCLKFREQ_SFT)
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#define MLB_CR_SET_CR_BCLKFREQ_SFT (8)
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#define MLB_CR_SET_CR_BCLKFREQ_MASK (0xFF << MLB_CR_SET_CR_BCLKFREQ_SFT)
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#define MLB_CR_SET_CR_RTUNTIMER_SFT (4)
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#define MLB_CR_SET_CR_RTUNTIMER_MASK (0xF << MLB_CR_SET_CR_RTUNTIMER_SFT)
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#define MLB_SD_TOCLK_I_DIV 16
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#define MLB_TOCLKFREQ_UNIT_THRES 16000000
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#define MLB_CAL_TOCLKFREQ_MHZ(rate) (rate / MLB_SD_TOCLK_I_DIV / 1000000)
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#define MLB_CAL_TOCLKFREQ_KHZ(rate) (rate / MLB_SD_TOCLK_I_DIV / 1000)
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#define MLB_TOCLKFREQ_MAX 63
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#define MLB_TOCLKFREQ_MIN 1
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#define MLB_SD_BCLK_I_DIV 4
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#define MLB_CAL_BCLKFREQ(rate) (rate / MLB_SD_BCLK_I_DIV / 1000000)
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#define MLB_BCLKFREQ_MAX 255
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#define MLB_BCLKFREQ_MIN 1
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#define MLB_CDR_SET 0x0230
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#define MLB_CDR_SET_CLK2POW16 3
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struct f_sdhost_priv {
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struct clk *clk_iface;
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struct clk *clk;
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struct device *dev;
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bool enable_cmd_dat_delay;
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};
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static void sdhci_milbeaut_soft_voltage_switch(struct sdhci_host *host)
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{
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u32 ctrl = 0;
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usleep_range(2500, 3000);
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ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
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ctrl |= F_SDH30_CRES_O_DN;
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sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
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ctrl |= F_SDH30_MSEL_O_1_8;
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sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
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ctrl &= ~F_SDH30_CRES_O_DN;
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sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
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usleep_range(2500, 3000);
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ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING);
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ctrl |= F_SDH30_CMD_CHK_DIS;
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sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING);
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}
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static unsigned int sdhci_milbeaut_get_min_clock(struct sdhci_host *host)
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{
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return F_SDH30_MIN_CLOCK;
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}
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static void sdhci_milbeaut_reset(struct sdhci_host *host, u8 mask)
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{
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struct f_sdhost_priv *priv = sdhci_priv(host);
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u16 clk;
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u32 ctl;
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ktime_t timeout;
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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clk = (clk & ~SDHCI_CLOCK_CARD_EN) | SDHCI_CLOCK_INT_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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sdhci_reset(host, mask);
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clk |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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timeout = ktime_add_ms(ktime_get(), 10);
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while (1) {
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bool timedout = ktime_after(ktime_get(), timeout);
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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if (clk & SDHCI_CLOCK_INT_STABLE)
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break;
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if (timedout) {
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pr_err("%s: Internal clock never stabilised.\n",
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mmc_hostname(host->mmc));
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sdhci_dumpregs(host);
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return;
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}
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udelay(10);
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}
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if (priv->enable_cmd_dat_delay) {
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ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
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ctl |= F_SDH30_CMD_DAT_DELAY;
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sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
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}
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}
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static const struct sdhci_ops sdhci_milbeaut_ops = {
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.voltage_switch = sdhci_milbeaut_soft_voltage_switch,
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.get_min_clock = sdhci_milbeaut_get_min_clock,
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.reset = sdhci_milbeaut_reset,
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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.set_power = sdhci_set_power_and_bus_voltage,
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};
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static void sdhci_milbeaut_bridge_reset(struct sdhci_host *host,
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int reset_flag)
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{
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if (reset_flag)
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sdhci_writel(host, 0, MLB_SOFT_RESET);
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else
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sdhci_writel(host, MLB_SOFT_RESET_RSTX, MLB_SOFT_RESET);
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}
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static void sdhci_milbeaut_bridge_init(struct sdhci_host *host,
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int rate)
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{
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u32 val, clk;
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/* IO_SDIO_CR_SET should be set while reset */
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val = sdhci_readl(host, MLB_CR_SET);
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val &= ~(MLB_CR_SET_CR_TOCLKFREQ_MASK | MLB_CR_SET_CR_TOCLKUNIT |
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MLB_CR_SET_CR_BCLKFREQ_MASK);
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if (rate >= MLB_TOCLKFREQ_UNIT_THRES) {
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clk = MLB_CAL_TOCLKFREQ_MHZ(rate);
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clk = min_t(u32, MLB_TOCLKFREQ_MAX, clk);
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val |= MLB_CR_SET_CR_TOCLKUNIT |
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(clk << MLB_CR_SET_CR_TOCLKFREQ_SFT);
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} else {
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clk = MLB_CAL_TOCLKFREQ_KHZ(rate);
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clk = min_t(u32, MLB_TOCLKFREQ_MAX, clk);
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clk = max_t(u32, MLB_TOCLKFREQ_MIN, clk);
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val |= clk << MLB_CR_SET_CR_TOCLKFREQ_SFT;
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}
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clk = MLB_CAL_BCLKFREQ(rate);
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clk = min_t(u32, MLB_BCLKFREQ_MAX, clk);
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clk = max_t(u32, MLB_BCLKFREQ_MIN, clk);
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val |= clk << MLB_CR_SET_CR_BCLKFREQ_SFT;
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val &= ~MLB_CR_SET_CR_RTUNTIMER_MASK;
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sdhci_writel(host, val, MLB_CR_SET);
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sdhci_writel(host, MLB_CDR_SET_CLK2POW16, MLB_CDR_SET);
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sdhci_writel(host, MLB_WP_CD_LED_SET_LED_INV, MLB_WP_CD_LED_SET);
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}
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static void sdhci_milbeaut_vendor_init(struct sdhci_host *host)
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{
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struct f_sdhost_priv *priv = sdhci_priv(host);
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u32 ctl;
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ctl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
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ctl |= F_SDH30_CRES_O_DN;
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sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2);
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ctl &= ~F_SDH30_MSEL_O_1_8;
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sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2);
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ctl &= ~F_SDH30_CRES_O_DN;
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sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2);
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ctl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
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ctl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
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F_SDH30_AHB_INCR_4;
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ctl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN);
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sdhci_writew(host, ctl, F_SDH30_AHB_CONFIG);
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if (priv->enable_cmd_dat_delay) {
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ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
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ctl |= F_SDH30_CMD_DAT_DELAY;
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sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
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}
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}
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static const struct of_device_id mlb_dt_ids[] = {
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{
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.compatible = "socionext,milbeaut-m10v-sdhci-3.0",
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, mlb_dt_ids);
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static void sdhci_milbeaut_init(struct sdhci_host *host)
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{
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struct f_sdhost_priv *priv = sdhci_priv(host);
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int rate = clk_get_rate(priv->clk);
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u16 ctl;
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sdhci_milbeaut_bridge_reset(host, 0);
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ctl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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ctl &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
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sdhci_writew(host, ctl, SDHCI_CLOCK_CONTROL);
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sdhci_milbeaut_bridge_reset(host, 1);
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sdhci_milbeaut_bridge_init(host, rate);
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sdhci_milbeaut_bridge_reset(host, 0);
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sdhci_milbeaut_vendor_init(host);
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}
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static int sdhci_milbeaut_probe(struct platform_device *pdev)
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{
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struct sdhci_host *host;
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struct device *dev = &pdev->dev;
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int irq, ret = 0;
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struct f_sdhost_priv *priv;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv));
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if (IS_ERR(host))
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return PTR_ERR(host);
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priv = sdhci_priv(host);
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priv->dev = dev;
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host->quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
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SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
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SDHCI_QUIRK_CLOCK_BEFORE_RESET |
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SDHCI_QUIRK_DELAY_AFTER_POWER;
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host->quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE |
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SDHCI_QUIRK2_TUNING_WORK_AROUND |
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SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
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priv->enable_cmd_dat_delay = device_property_read_bool(dev,
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"fujitsu,cmd-dat-delay-select");
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ret = mmc_of_parse(host->mmc);
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if (ret)
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goto err;
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platform_set_drvdata(pdev, host);
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host->hw_name = "f_sdh30";
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host->ops = &sdhci_milbeaut_ops;
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host->irq = irq;
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host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(host->ioaddr)) {
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ret = PTR_ERR(host->ioaddr);
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goto err;
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}
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if (dev_of_node(dev)) {
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sdhci_get_of_property(pdev);
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priv->clk_iface = devm_clk_get(&pdev->dev, "iface");
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if (IS_ERR(priv->clk_iface)) {
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ret = PTR_ERR(priv->clk_iface);
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goto err;
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}
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ret = clk_prepare_enable(priv->clk_iface);
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if (ret)
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goto err;
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priv->clk = devm_clk_get(&pdev->dev, "core");
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if (IS_ERR(priv->clk)) {
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ret = PTR_ERR(priv->clk);
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goto err_clk;
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}
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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goto err_clk;
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}
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sdhci_milbeaut_init(host);
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ret = sdhci_add_host(host);
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if (ret)
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goto err_add_host;
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return 0;
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err_add_host:
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clk_disable_unprepare(priv->clk);
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err_clk:
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clk_disable_unprepare(priv->clk_iface);
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err:
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sdhci_free_host(host);
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return ret;
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}
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static int sdhci_milbeaut_remove(struct platform_device *pdev)
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{
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struct sdhci_host *host = platform_get_drvdata(pdev);
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struct f_sdhost_priv *priv = sdhci_priv(host);
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sdhci_remove_host(host, readl(host->ioaddr + SDHCI_INT_STATUS) ==
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0xffffffff);
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clk_disable_unprepare(priv->clk_iface);
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clk_disable_unprepare(priv->clk);
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sdhci_free_host(host);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver sdhci_milbeaut_driver = {
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.driver = {
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.name = "sdhci-milbeaut",
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
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.of_match_table = of_match_ptr(mlb_dt_ids),
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},
|
||
|
|
.probe = sdhci_milbeaut_probe,
|
||
|
|
.remove = sdhci_milbeaut_remove,
|
||
|
|
};
|
||
|
|
|
||
|
|
module_platform_driver(sdhci_milbeaut_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("MILBEAUT SD Card Controller driver");
|
||
|
|
MODULE_AUTHOR("Takao Orito <orito.takao@socionext.com>");
|
||
|
|
MODULE_LICENSE("GPL v2");
|
||
|
|
MODULE_ALIAS("platform:sdhci-milbeaut");
|