452 lines
13 KiB
C
452 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* BCM47XX NAND flash driver
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*
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* Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
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*/
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#include "bcm47xxnflash.h"
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/bcma/bcma.h>
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/* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has
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* shown ~1000 retries as maximum. */
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#define NFLASH_READY_RETRIES 10000
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#define NFLASH_SECTOR_SIZE 512
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#define NCTL_CMD0 0x00010000
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#define NCTL_COL 0x00020000 /* Update column with value from BCMA_CC_NFLASH_COL_ADDR */
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#define NCTL_ROW 0x00040000 /* Update row (page) with value from BCMA_CC_NFLASH_ROW_ADDR */
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#define NCTL_CMD1W 0x00080000
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#define NCTL_READ 0x00100000
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#define NCTL_WRITE 0x00200000
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#define NCTL_SPECADDR 0x01000000
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#define NCTL_READY 0x04000000
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#define NCTL_ERR 0x08000000
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#define NCTL_CSA 0x40000000
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#define NCTL_START 0x80000000
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/**************************************************
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* Various helpers
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**************************************************/
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static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
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{
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return ((ns * 1000 * clock) / 1000000) + 1;
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}
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static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
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{
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int i = 0;
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bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, NCTL_START | code);
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for (i = 0; i < NFLASH_READY_RETRIES; i++) {
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if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_START)) {
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i = 0;
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break;
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}
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}
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if (i) {
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pr_err("NFLASH control command not ready!\n");
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return -EBUSY;
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}
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return 0;
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}
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static int bcm47xxnflash_ops_bcm4706_poll(struct bcma_drv_cc *cc)
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{
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int i;
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for (i = 0; i < NFLASH_READY_RETRIES; i++) {
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if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_READY) {
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if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) &
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BCMA_CC_NFLASH_CTL_ERR) {
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pr_err("Error on polling\n");
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return -EBUSY;
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} else {
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return 0;
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}
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}
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}
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pr_err("Polling timeout!\n");
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return -EBUSY;
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}
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/**************************************************
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* R/W
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**************************************************/
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static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,
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int len)
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{
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struct nand_chip *nand_chip = mtd_to_nand(mtd);
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struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
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u32 ctlcode;
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u32 *dest = (u32 *)buf;
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int i;
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int toread;
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BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
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/* Don't validate column using nand_chip->page_shift, it may be bigger
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* when accessing OOB */
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while (len) {
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/* We can read maximum of 0x200 bytes at once */
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toread = min(len, 0x200);
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/* Set page and column */
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bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_COL_ADDR,
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b47n->curr_column);
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bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_ROW_ADDR,
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b47n->curr_page_addr);
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/* Prepare to read */
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ctlcode = NCTL_CSA | NCTL_CMD1W | NCTL_ROW | NCTL_COL |
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NCTL_CMD0;
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ctlcode |= NAND_CMD_READSTART << 8;
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if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode))
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return;
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if (bcm47xxnflash_ops_bcm4706_poll(b47n->cc))
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return;
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/* Eventually read some data :) */
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for (i = 0; i < toread; i += 4, dest++) {
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ctlcode = NCTL_CSA | 0x30000000 | NCTL_READ;
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if (i == toread - 4) /* Last read goes without that */
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ctlcode &= ~NCTL_CSA;
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if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
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ctlcode))
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return;
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*dest = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA);
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}
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b47n->curr_column += toread;
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len -= toread;
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}
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}
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static void bcm47xxnflash_ops_bcm4706_write(struct mtd_info *mtd,
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const uint8_t *buf, int len)
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{
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struct nand_chip *nand_chip = mtd_to_nand(mtd);
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struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
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struct bcma_drv_cc *cc = b47n->cc;
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u32 ctlcode;
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const u32 *data = (u32 *)buf;
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int i;
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BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
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/* Don't validate column using nand_chip->page_shift, it may be bigger
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* when accessing OOB */
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for (i = 0; i < len; i += 4, data++) {
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bcma_cc_write32(cc, BCMA_CC_NFLASH_DATA, *data);
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ctlcode = NCTL_CSA | 0x30000000 | NCTL_WRITE;
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if (i == len - 4) /* Last read goes without that */
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ctlcode &= ~NCTL_CSA;
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if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode)) {
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pr_err("%s ctl_cmd didn't work!\n", __func__);
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return;
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}
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}
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b47n->curr_column += len;
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}
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/**************************************************
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* NAND chip ops
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**************************************************/
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static void bcm47xxnflash_ops_bcm4706_cmd_ctrl(struct nand_chip *nand_chip,
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int cmd, unsigned int ctrl)
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{
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struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
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u32 code = 0;
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if (cmd == NAND_CMD_NONE)
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return;
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if (cmd & NAND_CTRL_CLE)
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code = cmd | NCTL_CMD0;
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/* nCS is not needed for reset command */
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if (cmd != NAND_CMD_RESET)
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code |= NCTL_CSA;
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bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, code);
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}
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/* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */
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static void bcm47xxnflash_ops_bcm4706_select_chip(struct nand_chip *chip,
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int cs)
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{
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return;
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}
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static int bcm47xxnflash_ops_bcm4706_dev_ready(struct nand_chip *nand_chip)
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{
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struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
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return !!(bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_CTL) & NCTL_READY);
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}
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/*
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* Default nand_command and nand_command_lp don't match BCM4706 hardware layout.
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* For example, reading chip id is performed in a non-standard way.
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* Setting column and page is also handled differently, we use a special
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* registers of ChipCommon core. Hacking cmd_ctrl to understand and convert
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* standard commands would be much more complicated.
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*/
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static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct nand_chip *nand_chip,
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unsigned command, int column,
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int page_addr)
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{
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struct mtd_info *mtd = nand_to_mtd(nand_chip);
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struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
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struct bcma_drv_cc *cc = b47n->cc;
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u32 ctlcode;
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int i;
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if (column != -1)
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b47n->curr_column = column;
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if (page_addr != -1)
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b47n->curr_page_addr = page_addr;
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switch (command) {
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case NAND_CMD_RESET:
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nand_chip->legacy.cmd_ctrl(nand_chip, command, NAND_CTRL_CLE);
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ndelay(100);
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nand_wait_ready(nand_chip);
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break;
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case NAND_CMD_READID:
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ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0;
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ctlcode |= NAND_CMD_READID;
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if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) {
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pr_err("READID error\n");
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break;
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}
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/*
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* Reading is specific, last one has to go without NCTL_CSA
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* bit. We don't know how many reads NAND subsystem is going
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* to perform, so cache everything.
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*/
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for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) {
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ctlcode = NCTL_CSA | NCTL_READ;
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if (i == ARRAY_SIZE(b47n->id_data) - 1)
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ctlcode &= ~NCTL_CSA;
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if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
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ctlcode)) {
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pr_err("READID error\n");
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break;
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}
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b47n->id_data[i] =
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bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA)
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& 0xFF;
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}
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break;
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case NAND_CMD_STATUS:
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ctlcode = NCTL_CSA | NCTL_CMD0 | NAND_CMD_STATUS;
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if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
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pr_err("STATUS command error\n");
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break;
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case NAND_CMD_READ0:
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break;
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case NAND_CMD_READOOB:
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if (page_addr != -1)
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b47n->curr_column += mtd->writesize;
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break;
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case NAND_CMD_ERASE1:
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bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR,
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b47n->curr_page_addr);
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ctlcode = NCTL_ROW | NCTL_CMD1W | NCTL_CMD0 |
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NAND_CMD_ERASE1 | (NAND_CMD_ERASE2 << 8);
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if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
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pr_err("ERASE1 failed\n");
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break;
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case NAND_CMD_ERASE2:
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break;
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case NAND_CMD_SEQIN:
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/* Set page and column */
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bcma_cc_write32(cc, BCMA_CC_NFLASH_COL_ADDR,
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b47n->curr_column);
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bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR,
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b47n->curr_page_addr);
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/* Prepare to write */
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ctlcode = 0x40000000 | NCTL_ROW | NCTL_COL | NCTL_CMD0;
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ctlcode |= NAND_CMD_SEQIN;
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if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
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pr_err("SEQIN failed\n");
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break;
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case NAND_CMD_PAGEPROG:
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if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, NCTL_CMD0 |
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NAND_CMD_PAGEPROG))
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pr_err("PAGEPROG failed\n");
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if (bcm47xxnflash_ops_bcm4706_poll(cc))
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pr_err("PAGEPROG not ready\n");
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break;
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default:
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pr_err("Command 0x%X unsupported\n", command);
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break;
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}
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b47n->curr_command = command;
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}
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static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct nand_chip *nand_chip)
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{
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struct mtd_info *mtd = nand_to_mtd(nand_chip);
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struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
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struct bcma_drv_cc *cc = b47n->cc;
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u32 tmp = 0;
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switch (b47n->curr_command) {
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case NAND_CMD_READID:
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if (b47n->curr_column >= ARRAY_SIZE(b47n->id_data)) {
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pr_err("Requested invalid id_data: %d\n",
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b47n->curr_column);
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return 0;
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}
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return b47n->id_data[b47n->curr_column++];
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case NAND_CMD_STATUS:
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if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, NCTL_READ))
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return 0;
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return bcma_cc_read32(cc, BCMA_CC_NFLASH_DATA) & 0xff;
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case NAND_CMD_READOOB:
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bcm47xxnflash_ops_bcm4706_read(mtd, (u8 *)&tmp, 4);
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return tmp & 0xFF;
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}
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pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command);
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return 0;
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}
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static void bcm47xxnflash_ops_bcm4706_read_buf(struct nand_chip *nand_chip,
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uint8_t *buf, int len)
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{
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struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
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switch (b47n->curr_command) {
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case NAND_CMD_READ0:
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case NAND_CMD_READOOB:
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bcm47xxnflash_ops_bcm4706_read(nand_to_mtd(nand_chip), buf,
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|
len);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void bcm47xxnflash_ops_bcm4706_write_buf(struct nand_chip *nand_chip,
|
||
|
|
const uint8_t *buf, int len)
|
||
|
|
{
|
||
|
|
struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
|
||
|
|
|
||
|
|
switch (b47n->curr_command) {
|
||
|
|
case NAND_CMD_SEQIN:
|
||
|
|
bcm47xxnflash_ops_bcm4706_write(nand_to_mtd(nand_chip), buf,
|
||
|
|
len);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
pr_err("Invalid command for buf write: 0x%X\n", b47n->curr_command);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**************************************************
|
||
|
|
* Init
|
||
|
|
**************************************************/
|
||
|
|
|
||
|
|
int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
|
||
|
|
{
|
||
|
|
struct nand_chip *nand_chip = (struct nand_chip *)&b47n->nand_chip;
|
||
|
|
int err;
|
||
|
|
u32 freq;
|
||
|
|
u16 clock;
|
||
|
|
u8 w0, w1, w2, w3, w4;
|
||
|
|
|
||
|
|
unsigned long chipsize; /* MiB */
|
||
|
|
u8 tbits, col_bits, col_size, row_bits, row_bsize;
|
||
|
|
u32 val;
|
||
|
|
|
||
|
|
nand_chip->legacy.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
|
||
|
|
nand_chip->legacy.cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl;
|
||
|
|
nand_chip->legacy.dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready;
|
||
|
|
b47n->nand_chip.legacy.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
|
||
|
|
b47n->nand_chip.legacy.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
|
||
|
|
b47n->nand_chip.legacy.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
|
||
|
|
b47n->nand_chip.legacy.write_buf = bcm47xxnflash_ops_bcm4706_write_buf;
|
||
|
|
b47n->nand_chip.legacy.set_features = nand_get_set_features_notsupp;
|
||
|
|
b47n->nand_chip.legacy.get_features = nand_get_set_features_notsupp;
|
||
|
|
|
||
|
|
nand_chip->legacy.chip_delay = 50;
|
||
|
|
b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
|
||
|
|
/* TODO: implement ECC */
|
||
|
|
b47n->nand_chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_NONE;
|
||
|
|
|
||
|
|
/* Enable NAND flash access */
|
||
|
|
bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
|
||
|
|
BCMA_CC_4706_FLASHSCFG_NF1);
|
||
|
|
|
||
|
|
/* Configure wait counters */
|
||
|
|
if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) {
|
||
|
|
/* 400 MHz */
|
||
|
|
freq = 400000000 / 4;
|
||
|
|
} else {
|
||
|
|
freq = bcma_chipco_pll_read(b47n->cc, 4);
|
||
|
|
freq = (freq & 0xFFF) >> 3;
|
||
|
|
/* Fixed reference clock 25 MHz and m = 2 */
|
||
|
|
freq = (freq * 25000000 / 2) / 4;
|
||
|
|
}
|
||
|
|
clock = freq / 1000000;
|
||
|
|
w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock);
|
||
|
|
w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock);
|
||
|
|
w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
|
||
|
|
w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
|
||
|
|
w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock);
|
||
|
|
bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0,
|
||
|
|
(w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
|
||
|
|
|
||
|
|
/* Scan NAND */
|
||
|
|
err = nand_scan(&b47n->nand_chip, 1);
|
||
|
|
if (err) {
|
||
|
|
pr_err("Could not scan NAND flash: %d\n", err);
|
||
|
|
goto exit;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Configure FLASH */
|
||
|
|
chipsize = nanddev_target_size(&b47n->nand_chip.base) >> 20;
|
||
|
|
tbits = ffs(chipsize); /* find first bit set */
|
||
|
|
if (!tbits || tbits != fls(chipsize)) {
|
||
|
|
pr_err("Invalid flash size: 0x%lX\n", chipsize);
|
||
|
|
err = -ENOTSUPP;
|
||
|
|
goto exit;
|
||
|
|
}
|
||
|
|
tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
|
||
|
|
|
||
|
|
col_bits = b47n->nand_chip.page_shift + 1;
|
||
|
|
col_size = (col_bits + 7) / 8;
|
||
|
|
|
||
|
|
row_bits = tbits - col_bits + 1;
|
||
|
|
row_bsize = (row_bits + 7) / 8;
|
||
|
|
|
||
|
|
val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2;
|
||
|
|
bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
|
||
|
|
|
||
|
|
exit:
|
||
|
|
if (err)
|
||
|
|
bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
|
||
|
|
~BCMA_CC_4706_FLASHSCFG_NF1);
|
||
|
|
return err;
|
||
|
|
}
|