250 lines
6.4 KiB
C
250 lines
6.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
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/*
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* Northstar Plus switch SerDes/SGMII PHY main logic
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*
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* Copyright (C) 2018 Florian Fainelli <f.fainelli@gmail.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/phy.h>
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#include <linux/phylink.h>
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#include <net/dsa.h>
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#include "b53_priv.h"
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#include "b53_serdes.h"
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#include "b53_regs.h"
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static inline struct b53_pcs *pcs_to_b53_pcs(struct phylink_pcs *pcs)
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{
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return container_of(pcs, struct b53_pcs, pcs);
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}
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static void b53_serdes_write_blk(struct b53_device *dev, u8 offset, u16 block,
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u16 value)
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{
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b53_write16(dev, B53_SERDES_PAGE, B53_SERDES_BLKADDR, block);
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b53_write16(dev, B53_SERDES_PAGE, offset, value);
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}
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static u16 b53_serdes_read_blk(struct b53_device *dev, u8 offset, u16 block)
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{
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u16 value;
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b53_write16(dev, B53_SERDES_PAGE, B53_SERDES_BLKADDR, block);
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b53_read16(dev, B53_SERDES_PAGE, offset, &value);
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return value;
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}
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static void b53_serdes_set_lane(struct b53_device *dev, u8 lane)
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{
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if (dev->serdes_lane == lane)
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return;
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WARN_ON(lane > 1);
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b53_serdes_write_blk(dev, B53_SERDES_LANE,
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SERDES_XGXSBLK0_BLOCKADDRESS, lane);
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dev->serdes_lane = lane;
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}
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static void b53_serdes_write(struct b53_device *dev, u8 lane,
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u8 offset, u16 block, u16 value)
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{
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b53_serdes_set_lane(dev, lane);
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b53_serdes_write_blk(dev, offset, block, value);
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}
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static u16 b53_serdes_read(struct b53_device *dev, u8 lane,
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u8 offset, u16 block)
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{
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b53_serdes_set_lane(dev, lane);
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return b53_serdes_read_blk(dev, offset, block);
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}
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static int b53_serdes_config(struct phylink_pcs *pcs, unsigned int mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev;
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u8 lane = pcs_to_b53_pcs(pcs)->lane;
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u16 reg;
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reg = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_CONTROL(1),
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SERDES_DIGITAL_BLK);
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if (interface == PHY_INTERFACE_MODE_1000BASEX)
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reg |= FIBER_MODE_1000X;
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else
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reg &= ~FIBER_MODE_1000X;
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b53_serdes_write(dev, lane, B53_SERDES_DIGITAL_CONTROL(1),
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SERDES_DIGITAL_BLK, reg);
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return 0;
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}
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static void b53_serdes_an_restart(struct phylink_pcs *pcs)
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{
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struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev;
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u8 lane = pcs_to_b53_pcs(pcs)->lane;
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u16 reg;
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reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
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SERDES_MII_BLK);
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reg |= BMCR_ANRESTART;
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b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
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SERDES_MII_BLK, reg);
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}
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static void b53_serdes_get_state(struct phylink_pcs *pcs,
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struct phylink_link_state *state)
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{
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struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev;
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u8 lane = pcs_to_b53_pcs(pcs)->lane;
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u16 dig, bmsr;
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dig = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_STATUS,
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SERDES_DIGITAL_BLK);
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bmsr = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMSR),
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SERDES_MII_BLK);
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switch ((dig >> SPEED_STATUS_SHIFT) & SPEED_STATUS_MASK) {
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case SPEED_STATUS_10:
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state->speed = SPEED_10;
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break;
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case SPEED_STATUS_100:
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state->speed = SPEED_100;
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break;
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case SPEED_STATUS_1000:
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state->speed = SPEED_1000;
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break;
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default:
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case SPEED_STATUS_2500:
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state->speed = SPEED_2500;
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break;
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}
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state->duplex = dig & DUPLEX_STATUS ? DUPLEX_FULL : DUPLEX_HALF;
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state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
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state->link = !!(dig & LINK_STATUS);
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if (dig & PAUSE_RESOLUTION_RX_SIDE)
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state->pause |= MLO_PAUSE_RX;
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if (dig & PAUSE_RESOLUTION_TX_SIDE)
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state->pause |= MLO_PAUSE_TX;
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}
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void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
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phy_interface_t interface, bool link_up)
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{
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u8 lane = b53_serdes_map_lane(dev, port);
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u16 reg;
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if (lane == B53_INVALID_LANE)
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return;
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reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
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SERDES_MII_BLK);
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if (link_up)
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reg &= ~BMCR_PDOWN;
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else
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reg |= BMCR_PDOWN;
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b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
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SERDES_MII_BLK, reg);
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}
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EXPORT_SYMBOL(b53_serdes_link_set);
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static const struct phylink_pcs_ops b53_pcs_ops = {
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.pcs_get_state = b53_serdes_get_state,
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.pcs_config = b53_serdes_config,
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.pcs_an_restart = b53_serdes_an_restart,
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};
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void b53_serdes_phylink_get_caps(struct b53_device *dev, int port,
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struct phylink_config *config)
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{
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u8 lane = b53_serdes_map_lane(dev, port);
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if (lane == B53_INVALID_LANE)
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return;
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switch (lane) {
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case 0:
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/* It appears lane 0 supports 2500base-X and 1000base-X */
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__set_bit(PHY_INTERFACE_MODE_2500BASEX,
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config->supported_interfaces);
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config->mac_capabilities |= MAC_2500FD;
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fallthrough;
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case 1:
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/* It appears lane 1 only supports 1000base-X and SGMII */
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__set_bit(PHY_INTERFACE_MODE_1000BASEX,
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config->supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_SGMII,
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config->supported_interfaces);
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config->mac_capabilities |= MAC_1000FD;
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break;
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default:
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break;
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}
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}
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EXPORT_SYMBOL(b53_serdes_phylink_get_caps);
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struct phylink_pcs *b53_serdes_phylink_mac_select_pcs(struct b53_device *dev,
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int port,
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phy_interface_t interface)
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{
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u8 lane = b53_serdes_map_lane(dev, port);
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if (lane == B53_INVALID_LANE || lane >= B53_N_PCS ||
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!dev->pcs[lane].dev)
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return NULL;
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if (!phy_interface_mode_is_8023z(interface) &&
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interface != PHY_INTERFACE_MODE_SGMII)
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return NULL;
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return &dev->pcs[lane].pcs;
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}
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EXPORT_SYMBOL(b53_serdes_phylink_mac_select_pcs);
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int b53_serdes_init(struct b53_device *dev, int port)
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{
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u8 lane = b53_serdes_map_lane(dev, port);
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struct b53_pcs *pcs;
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u16 id0, msb, lsb;
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if (lane == B53_INVALID_LANE)
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return -EINVAL;
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id0 = b53_serdes_read(dev, lane, B53_SERDES_ID0, SERDES_ID0);
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msb = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_PHYSID1),
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SERDES_MII_BLK);
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lsb = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_PHYSID2),
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SERDES_MII_BLK);
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if (id0 == 0 || id0 == 0xffff) {
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dev_err(dev->dev, "SerDes not initialized, check settings\n");
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return -ENODEV;
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}
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dev_info(dev->dev,
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"SerDes lane %d, model: %d, rev %c%d (OUI: 0x%08x)\n",
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lane, id0 & SERDES_ID0_MODEL_MASK,
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(id0 >> SERDES_ID0_REV_LETTER_SHIFT) + 0x41,
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(id0 >> SERDES_ID0_REV_NUM_SHIFT) & SERDES_ID0_REV_NUM_MASK,
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(u32)msb << 16 | lsb);
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pcs = &dev->pcs[lane];
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pcs->dev = dev;
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pcs->lane = lane;
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pcs->pcs.ops = &b53_pcs_ops;
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return 0;
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}
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EXPORT_SYMBOL(b53_serdes_init);
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MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
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MODULE_DESCRIPTION("B53 Switch SerDes driver");
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MODULE_LICENSE("Dual BSD/GPL");
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