387 lines
15 KiB
C
387 lines
15 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Marvell 88E6xxx Switch Global 2 Registers support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2016-2017 Savoir-faire Linux Inc.
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* Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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*/
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#ifndef _MV88E6XXX_GLOBAL2_H
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#define _MV88E6XXX_GLOBAL2_H
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#include "chip.h"
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/* Offset 0x00: Interrupt Source Register */
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#define MV88E6XXX_G2_INT_SRC 0x00
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#define MV88E6XXX_G2_INT_SRC_WDOG 0x8000
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#define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000
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#define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000
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#define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000
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#define MV88E6352_G2_INT_SRC_SERDES 0x0800
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#define MV88E6352_G2_INT_SRC_PHY 0x001f
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#define MV88E6390_G2_INT_SRC_PHY 0x07fe
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#define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15
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/* Offset 0x01: Interrupt Mask Register */
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#define MV88E6XXX_G2_INT_MASK 0x01
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#define MV88E6XXX_G2_INT_MASK_WDOG 0x8000
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#define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x4000
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#define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000
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#define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x1000
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#define MV88E6352_G2_INT_MASK_SERDES 0x0800
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#define MV88E6352_G2_INT_MASK_PHY 0x001f
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#define MV88E6390_G2_INT_MASK_PHY 0x07fe
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/* Offset 0x02: MGMT Enable Register 2x */
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#define MV88E6XXX_G2_MGMT_EN_2X 0x02
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/* Offset 0x02: MAC LINK change IRQ Register for MV88E6393X */
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#define MV88E6393X_G2_MACLINK_INT_SRC 0x02
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/* Offset 0x03: MGMT Enable Register 0x */
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#define MV88E6XXX_G2_MGMT_EN_0X 0x03
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/* Offset 0x03: MAC LINK change IRQ Mask Register for MV88E6393X */
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#define MV88E6393X_G2_MACLINK_INT_MASK 0x03
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/* Offset 0x04: Flow Control Delay Register */
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#define MV88E6XXX_G2_FLOW_CTL 0x04
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/* Offset 0x05: Switch Management Register */
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#define MV88E6XXX_G2_SWITCH_MGMT 0x05
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#define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000
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#define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000
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#define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000
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#define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080
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#define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008
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#define MV88E6393X_G2_EGRESS_MONITOR_DEST 0x05
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/* Offset 0x06: Device Mapping Table Register */
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#define MV88E6XXX_G2_DEVICE_MAPPING 0x06
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#define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000
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#define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00
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#define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK 0x000f
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#define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK 0x001f
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/* Offset 0x07: Trunk Mask Table Register */
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#define MV88E6XXX_G2_TRUNK_MASK 0x07
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#define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000
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#define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000
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#define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800
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/* Offset 0x08: Trunk Mapping Table Register */
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#define MV88E6XXX_G2_TRUNK_MAPPING 0x08
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#define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000
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#define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800
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/* Offset 0x09: Ingress Rate Command Register */
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#define MV88E6XXX_G2_IRL_CMD 0x09
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#define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000
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#define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000
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#define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000
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#define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000
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#define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000
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#define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000
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#define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000
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#define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000
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#define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000
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#define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000
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#define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000
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#define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000
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#define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00
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#define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00
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#define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0
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#define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f
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/* Offset 0x0A: Ingress Rate Data Register */
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#define MV88E6XXX_G2_IRL_DATA 0x0a
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#define MV88E6XXX_G2_IRL_DATA_MASK 0xffff
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/* Offset 0x0B: Cross-chip Port VLAN Register */
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#define MV88E6XXX_G2_PVT_ADDR 0x0b
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#define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000
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#define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000
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#define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000
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#define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000
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#define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000
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#define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff
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#define MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK 0x1f
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/* Offset 0x0C: Cross-chip Port VLAN Data Register */
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#define MV88E6XXX_G2_PVT_DATA 0x0c
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#define MV88E6XXX_G2_PVT_DATA_MASK 0x7f
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/* Offset 0x0D: Switch MAC/WoL/WoF Register */
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#define MV88E6XXX_G2_SWITCH_MAC 0x0d
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#define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000
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#define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00
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#define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff
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/* Offset 0x0E: ATU Stats Register */
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#define MV88E6XXX_G2_ATU_STATS 0x0e
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#define MV88E6XXX_G2_ATU_STATS_BIN_0 (0x0 << 14)
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#define MV88E6XXX_G2_ATU_STATS_BIN_1 (0x1 << 14)
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#define MV88E6XXX_G2_ATU_STATS_BIN_2 (0x2 << 14)
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#define MV88E6XXX_G2_ATU_STATS_BIN_3 (0x3 << 14)
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#define MV88E6XXX_G2_ATU_STATS_MODE_ALL (0x0 << 12)
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#define MV88E6XXX_G2_ATU_STATS_MODE_ALL_DYNAMIC (0x1 << 12)
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#define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL (0x2 << 12)
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#define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL_DYNAMIC (0x3 << 12)
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#define MV88E6XXX_G2_ATU_STATS_MASK 0x0fff
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/* Offset 0x0F: Priority Override Table */
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#define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f
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#define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000
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#define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000
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#define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00
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#define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080
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#define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030
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#define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008
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#define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007
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/* Offset 0x14: EEPROM Command */
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#define MV88E6XXX_G2_EEPROM_CMD 0x14
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#define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000
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#define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000
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#define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000
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#define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000
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#define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000
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#define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800
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#define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400
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#define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff
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#define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff
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/* Offset 0x15: EEPROM Data */
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#define MV88E6352_G2_EEPROM_DATA 0x15
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#define MV88E6352_G2_EEPROM_DATA_MASK 0xffff
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/* Offset 0x15: EEPROM Addr */
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#define MV88E6390_G2_EEPROM_ADDR 0x15
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#define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff
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/* Offset 0x16: AVB Command Register */
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#define MV88E6352_G2_AVB_CMD 0x16
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#define MV88E6352_G2_AVB_CMD_BUSY 0x8000
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#define MV88E6352_G2_AVB_CMD_OP_READ 0x4000
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#define MV88E6352_G2_AVB_CMD_OP_READ_INCR 0x6000
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#define MV88E6352_G2_AVB_CMD_OP_WRITE 0x3000
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#define MV88E6390_G2_AVB_CMD_OP_READ 0x0000
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#define MV88E6390_G2_AVB_CMD_OP_READ_INCR 0x4000
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#define MV88E6390_G2_AVB_CMD_OP_WRITE 0x6000
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#define MV88E6352_G2_AVB_CMD_PORT_MASK 0x0f00
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#define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL 0xe
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#define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL 0xf
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#define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL 0xf
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#define MV88E6390_G2_AVB_CMD_PORT_MASK 0x1f00
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#define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL 0x1e
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#define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL 0x1f
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#define MV88E6352_G2_AVB_CMD_BLOCK_PTP 0
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#define MV88E6352_G2_AVB_CMD_BLOCK_AVB 1
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#define MV88E6352_G2_AVB_CMD_BLOCK_QAV 2
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#define MV88E6352_G2_AVB_CMD_BLOCK_QVB 3
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#define MV88E6352_G2_AVB_CMD_BLOCK_MASK 0x00e0
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#define MV88E6352_G2_AVB_CMD_ADDR_MASK 0x001f
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/* Offset 0x17: AVB Data Register */
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#define MV88E6352_G2_AVB_DATA 0x17
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/* Offset 0x18: SMI PHY Command Register */
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#define MV88E6XXX_G2_SMI_PHY_CMD 0x18
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#define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000
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#define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000
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#define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000
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#define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000
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#define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000
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#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000
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#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000
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#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000
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#define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00
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#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400
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#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800
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#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000
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#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400
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#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800
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#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00
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#define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0
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#define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f
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#define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff
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/* Offset 0x19: SMI PHY Data Register */
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#define MV88E6XXX_G2_SMI_PHY_DATA 0x19
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/* Offset 0x1A: Scratch and Misc. Register */
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#define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a
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#define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000
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#define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00
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#define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff
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/* Offset 0x1B: Watch Dog Control Register */
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#define MV88E6250_G2_WDOG_CTL 0x1b
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#define MV88E6250_G2_WDOG_CTL_QC_HISTORY 0x0100
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#define MV88E6250_G2_WDOG_CTL_QC_EVENT 0x0080
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#define MV88E6250_G2_WDOG_CTL_QC_ENABLE 0x0040
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#define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY 0x0020
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#define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT 0x0010
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#define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE 0x0008
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#define MV88E6250_G2_WDOG_CTL_FORCE_IRQ 0x0004
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#define MV88E6250_G2_WDOG_CTL_HISTORY 0x0002
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#define MV88E6250_G2_WDOG_CTL_SWRESET 0x0001
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/* Offset 0x1B: Watch Dog Control Register */
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#define MV88E6352_G2_WDOG_CTL 0x1b
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#define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080
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#define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040
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#define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020
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#define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010
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#define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008
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#define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004
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#define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002
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#define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001
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/* Offset 0x1B: Watch Dog Control Register */
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#define MV88E6390_G2_WDOG_CTL 0x1b
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#define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000
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#define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00
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#define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000
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#define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000
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#define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100
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#define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200
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#define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300
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#define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff
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#define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008
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#define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004
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#define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002
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#define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001
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/* Offset 0x1C: QoS Weights Register */
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#define MV88E6XXX_G2_QOS_WEIGHTS 0x1c
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#define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000
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#define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00
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#define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00
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#define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff
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/* Offset 0x1D: Misc Register */
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#define MV88E6XXX_G2_MISC 0x1d
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#define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000
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#define MV88E6352_G2_NOEGR_POLICY 0x2000
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#define MV88E6390_G2_LAG_ID_4 0x2000
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/* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */
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/* Offset 0x02: Misc Configuration */
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#define MV88E6352_G2_SCRATCH_MISC_CFG 0x02
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#define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80
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/* Offset 0x60-0x61: GPIO Configuration */
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#define MV88E6352_G2_SCRATCH_GPIO_CFG0 0x60
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#define MV88E6352_G2_SCRATCH_GPIO_CFG1 0x61
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/* Offset 0x62-0x63: GPIO Direction */
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#define MV88E6352_G2_SCRATCH_GPIO_DIR0 0x62
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#define MV88E6352_G2_SCRATCH_GPIO_DIR1 0x63
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#define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT 0
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#define MV88E6352_G2_SCRATCH_GPIO_DIR_IN 1
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/* Offset 0x64-0x65: GPIO Data */
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#define MV88E6352_G2_SCRATCH_GPIO_DATA0 0x64
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#define MV88E6352_G2_SCRATCH_GPIO_DATA1 0x65
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/* Offset 0x68-0x6F: GPIO Pin Control */
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#define MV88E6352_G2_SCRATCH_GPIO_PCTL0 0x68
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#define MV88E6352_G2_SCRATCH_GPIO_PCTL1 0x69
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#define MV88E6352_G2_SCRATCH_GPIO_PCTL2 0x6A
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#define MV88E6352_G2_SCRATCH_GPIO_PCTL3 0x6B
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#define MV88E6352_G2_SCRATCH_GPIO_PCTL4 0x6C
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#define MV88E6352_G2_SCRATCH_GPIO_PCTL5 0x6D
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#define MV88E6352_G2_SCRATCH_GPIO_PCTL6 0x6E
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#define MV88E6352_G2_SCRATCH_GPIO_PCTL7 0x6F
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#define MV88E6352_G2_SCRATCH_CONFIG_DATA0 0x70
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#define MV88E6352_G2_SCRATCH_CONFIG_DATA1 0x71
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#define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2)
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||
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#define MV88E6352_G2_SCRATCH_CONFIG_DATA2 0x72
|
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#define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0xf
|
||
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#define MV88E6352_G2_SCRATCH_CONFIG_DATA3 0x73
|
||
|
|
#define MV88E6352_G2_SCRATCH_CONFIG_DATA3_S_SEL BIT(1)
|
||
|
|
|
||
|
|
#define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO 0
|
||
|
|
#define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG 1
|
||
|
|
#define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ 2
|
||
|
|
|
||
|
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int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
|
||
|
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int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
|
||
|
|
int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg,
|
||
|
|
int bit, int val);
|
||
|
|
|
||
|
|
int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
|
||
|
|
int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
|
||
|
|
|
||
|
|
int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip,
|
||
|
|
struct mii_bus *bus,
|
||
|
|
int addr, int reg, u16 *val);
|
||
|
|
int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip,
|
||
|
|
struct mii_bus *bus,
|
||
|
|
int addr, int reg, u16 val);
|
||
|
|
int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
|
||
|
|
struct mii_bus *bus,
|
||
|
|
int addr, int devad, int reg, u16 *val);
|
||
|
|
int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
|
||
|
|
struct mii_bus *bus,
|
||
|
|
int addr, int devad, int reg, u16 val);
|
||
|
|
int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
|
||
|
|
|
||
|
|
int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
|
||
|
|
struct ethtool_eeprom *eeprom, u8 *data);
|
||
|
|
int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
|
||
|
|
struct ethtool_eeprom *eeprom, u8 *data);
|
||
|
|
|
||
|
|
int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
|
||
|
|
struct ethtool_eeprom *eeprom, u8 *data);
|
||
|
|
int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
|
||
|
|
struct ethtool_eeprom *eeprom, u8 *data);
|
||
|
|
|
||
|
|
int mv88e6xxx_g2_pvt_read(struct mv88e6xxx_chip *chip, int src_dev,
|
||
|
|
int src_port, u16 *data);
|
||
|
|
int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
|
||
|
|
int src_port, u16 data);
|
||
|
|
int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip);
|
||
|
|
|
||
|
|
int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);
|
||
|
|
void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);
|
||
|
|
|
||
|
|
int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
|
||
|
|
struct mii_bus *bus);
|
||
|
|
void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
|
||
|
|
struct mii_bus *bus);
|
||
|
|
|
||
|
|
int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
|
||
|
|
int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
|
||
|
|
|
||
|
|
int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip);
|
||
|
|
|
||
|
|
int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
|
||
|
|
bool hash, u16 mask);
|
||
|
|
int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
|
||
|
|
u16 map);
|
||
|
|
int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip);
|
||
|
|
|
||
|
|
int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
|
||
|
|
int port);
|
||
|
|
|
||
|
|
extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;
|
||
|
|
extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops;
|
||
|
|
extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;
|
||
|
|
extern const struct mv88e6xxx_irq_ops mv88e6393x_watchdog_ops;
|
||
|
|
|
||
|
|
extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops;
|
||
|
|
extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops;
|
||
|
|
extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops;
|
||
|
|
|
||
|
|
extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;
|
||
|
|
|
||
|
|
int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
|
||
|
|
bool external);
|
||
|
|
int mv88e6352_g2_scratch_port_has_serdes(struct mv88e6xxx_chip *chip, int port);
|
||
|
|
int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin);
|
||
|
|
int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats);
|
||
|
|
|
||
|
|
#endif /* _MV88E6XXX_GLOBAL2_H */
|