400 lines
10 KiB
C
400 lines
10 KiB
C
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/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2016 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more details.
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***********************************************************************/
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/*! \file octeon_iq.h
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* \brief Host Driver: Implementation of Octeon input queues. "Input" is
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* with respect to the Octeon device on the NIC. From this driver's
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* point of view they are egress queues.
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*/
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#ifndef __OCTEON_IQ_H__
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#define __OCTEON_IQ_H__
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#define IQ_STATUS_RUNNING 1
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#define IQ_SEND_OK 0
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#define IQ_SEND_STOP 1
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#define IQ_SEND_FAILED -1
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/*------------------------- INSTRUCTION QUEUE --------------------------*/
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/* \cond */
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#define REQTYPE_NONE 0
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#define REQTYPE_NORESP_NET 1
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#define REQTYPE_NORESP_NET_SG 2
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#define REQTYPE_RESP_NET 3
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#define REQTYPE_RESP_NET_SG 4
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#define REQTYPE_SOFT_COMMAND 5
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#define REQTYPE_LAST 5
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struct octeon_request_list {
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u32 reqtype;
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void *buf;
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};
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/* \endcond */
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/** Input Queue statistics. Each input queue has four stats fields. */
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struct oct_iq_stats {
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u64 instr_posted; /**< Instructions posted to this queue. */
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u64 instr_processed; /**< Instructions processed in this queue. */
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u64 instr_dropped; /**< Instructions that could not be processed */
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u64 bytes_sent; /**< Bytes sent through this queue. */
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u64 sgentry_sent;/**< Gather entries sent through this queue. */
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u64 tx_done;/**< Num of packets sent to network. */
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u64 tx_iq_busy;/**< Numof times this iq was found to be full. */
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u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */
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u64 tx_tot_bytes;/**< Total count of bytes sento to network. */
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u64 tx_gso; /* count of tso */
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u64 tx_vxlan; /* tunnel */
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u64 tx_dmamap_fail; /* Number of times dma mapping failed */
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u64 tx_restart; /* Number of times this queue restarted */
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};
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#define OCT_IQ_STATS_SIZE (sizeof(struct oct_iq_stats))
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/** The instruction (input) queue.
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* The input queue is used to post raw (instruction) mode data or packet
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* data to Octeon device from the host. Each input queue (upto 4) for
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* a Octeon device has one such structure to represent it.
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*/
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struct octeon_instr_queue {
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struct octeon_device *oct_dev;
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/** A spinlock to protect access to the input ring. */
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spinlock_t lock;
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/** A spinlock to protect while posting on the ring. */
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spinlock_t post_lock;
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/** This flag indicates if the queue can be used for soft commands.
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* If this flag is set, post_lock must be acquired before posting
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* a command to the queue.
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* If this flag is clear, post_lock is invalid for the queue.
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* All control commands (soft commands) will go through only Queue 0
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* (control and data queue). So only queue-0 needs post_lock,
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* other queues are only data queues and does not need post_lock
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*/
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bool allow_soft_cmds;
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u32 pkt_in_done;
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u32 pkts_processed;
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/** A spinlock to protect access to the input ring.*/
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spinlock_t iq_flush_running_lock;
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/** Flag that indicates if the queue uses 64 byte commands. */
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u32 iqcmd_64B:1;
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/** Queue info. */
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union oct_txpciq txpciq;
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u32 rsvd:17;
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/* Controls whether extra flushing of IQ is done on Tx */
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u32 do_auto_flush:1;
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u32 status:8;
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/** Maximum no. of instructions in this queue. */
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u32 max_count;
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/** Index in input ring where the driver should write the next packet */
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u32 host_write_index;
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/** Index in input ring where Octeon is expected to read the next
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* packet.
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*/
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u32 octeon_read_index;
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/** This index aids in finding the window in the queue where Octeon
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* has read the commands.
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*/
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u32 flush_index;
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/** This field keeps track of the instructions pending in this queue. */
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atomic_t instr_pending;
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u32 reset_instr_cnt;
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/** Pointer to the Virtual Base addr of the input ring. */
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u8 *base_addr;
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struct octeon_request_list *request_list;
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/** Octeon doorbell register for the ring. */
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void __iomem *doorbell_reg;
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/** Octeon instruction count register for this ring. */
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void __iomem *inst_cnt_reg;
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/** Number of instructions pending to be posted to Octeon. */
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u32 fill_cnt;
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/** The max. number of instructions that can be held pending by the
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* driver.
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*/
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u32 fill_threshold;
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/** The last time that the doorbell was rung. */
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u64 last_db_time;
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/** The doorbell timeout. If the doorbell was not rung for this time and
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* fill_cnt is non-zero, ring the doorbell again.
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*/
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u32 db_timeout;
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/** Statistics for this input queue. */
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struct oct_iq_stats stats;
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/** DMA mapped base address of the input descriptor ring. */
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dma_addr_t base_addr_dma;
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/** Application context */
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void *app_ctx;
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/* network stack queue index */
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int q_index;
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/*os ifidx associated with this queue */
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int ifidx;
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};
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/*---------------------- INSTRUCTION FORMAT ----------------------------*/
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/** 32-byte instruction format.
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* Format of instruction for a 32-byte mode input queue.
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*/
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struct octeon_instr_32B {
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/** Pointer where the input data is available. */
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u64 dptr;
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/** Instruction Header. */
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u64 ih;
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/** Pointer where the response for a RAW mode packet will be written
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* by Octeon.
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*/
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u64 rptr;
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/** Input Request Header. Additional info about the input. */
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u64 irh;
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};
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#define OCT_32B_INSTR_SIZE (sizeof(struct octeon_instr_32B))
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/** 64-byte instruction format.
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* Format of instruction for a 64-byte mode input queue.
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*/
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struct octeon_instr2_64B {
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/** Pointer where the input data is available. */
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u64 dptr;
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/** Instruction Header. */
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u64 ih2;
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/** Input Request Header. */
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u64 irh;
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/** opcode/subcode specific parameters */
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u64 ossp[2];
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/** Return Data Parameters */
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u64 rdp;
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/** Pointer where the response for a RAW mode packet will be written
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* by Octeon.
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*/
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u64 rptr;
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u64 reserved;
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};
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struct octeon_instr3_64B {
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/** Pointer where the input data is available. */
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u64 dptr;
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/** Instruction Header. */
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u64 ih3;
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/** Instruction Header. */
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u64 pki_ih3;
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/** Input Request Header. */
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u64 irh;
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/** opcode/subcode specific parameters */
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u64 ossp[2];
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/** Return Data Parameters */
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u64 rdp;
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/** Pointer where the response for a RAW mode packet will be written
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* by Octeon.
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*/
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u64 rptr;
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};
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union octeon_instr_64B {
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struct octeon_instr2_64B cmd2;
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struct octeon_instr3_64B cmd3;
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};
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#define OCT_64B_INSTR_SIZE (sizeof(union octeon_instr_64B))
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/** The size of each buffer in soft command buffer pool
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*/
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#define SOFT_COMMAND_BUFFER_SIZE 2048
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struct octeon_soft_command {
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/** Soft command buffer info. */
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struct list_head node;
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u64 dma_addr;
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u32 size;
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/** Command and return status */
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union octeon_instr_64B cmd;
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#define COMPLETION_WORD_INIT 0xffffffffffffffffULL
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u64 *status_word;
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/** Data buffer info */
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void *virtdptr;
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u64 dmadptr;
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u32 datasize;
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/** Return buffer info */
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void *virtrptr;
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u64 dmarptr;
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u32 rdatasize;
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/** Context buffer info */
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void *ctxptr;
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u32 ctxsize;
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/** Time out and callback */
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size_t expiry_time;
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u32 iq_no;
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void (*callback)(struct octeon_device *, u32, void *);
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void *callback_arg;
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int caller_is_done;
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u32 sc_status;
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struct completion complete;
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};
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/* max timeout (in milli sec) for soft request */
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#define LIO_SC_MAX_TMO_MS 60000
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/** Maximum number of buffers to allocate into soft command buffer pool
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*/
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#define MAX_SOFT_COMMAND_BUFFERS 256
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/** Head of a soft command buffer pool.
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*/
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struct octeon_sc_buffer_pool {
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/** List structure to add delete pending entries to */
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struct list_head head;
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/** A lock for this response list */
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spinlock_t lock;
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atomic_t alloc_buf_count;
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};
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#define INCR_INSTRQUEUE_PKT_COUNT(octeon_dev_ptr, iq_no, field, count) \
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(((octeon_dev_ptr)->instr_queue[iq_no]->stats.field) += count)
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int octeon_setup_sc_buffer_pool(struct octeon_device *oct);
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int octeon_free_sc_done_list(struct octeon_device *oct);
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int octeon_free_sc_zombie_list(struct octeon_device *oct);
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int octeon_free_sc_buffer_pool(struct octeon_device *oct);
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struct octeon_soft_command *
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octeon_alloc_soft_command(struct octeon_device *oct,
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u32 datasize, u32 rdatasize,
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u32 ctxsize);
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void octeon_free_soft_command(struct octeon_device *oct,
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struct octeon_soft_command *sc);
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/**
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* octeon_init_instr_queue()
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* @param octeon_dev - pointer to the octeon device structure.
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* @param txpciq - queue to be initialized (0 <= q_no <= 3).
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*
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* Called at driver init time for each input queue. iq_conf has the
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* configuration parameters for the queue.
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*
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* @return Success: 0 Failure: 1
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*/
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int octeon_init_instr_queue(struct octeon_device *octeon_dev,
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union oct_txpciq txpciq,
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u32 num_descs);
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/**
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* octeon_delete_instr_queue()
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* @param octeon_dev - pointer to the octeon device structure.
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* @param iq_no - queue to be deleted (0 <= q_no <= 3).
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*
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* Called at driver unload time for each input queue. Deletes all
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* allocated resources for the input queue.
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*
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* @return Success: 0 Failure: 1
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*/
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int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no);
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int lio_wait_for_instr_fetch(struct octeon_device *oct);
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void
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octeon_ring_doorbell_locked(struct octeon_device *oct, u32 iq_no);
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int
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octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype,
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void (*fn)(void *));
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int
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lio_process_iq_request_list(struct octeon_device *oct,
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struct octeon_instr_queue *iq, u32 napi_budget);
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int octeon_send_command(struct octeon_device *oct, u32 iq_no,
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u32 force_db, void *cmd, void *buf,
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u32 datasize, u32 reqtype);
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void octeon_dump_soft_command(struct octeon_device *oct,
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struct octeon_soft_command *sc);
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void octeon_prepare_soft_command(struct octeon_device *oct,
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struct octeon_soft_command *sc,
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u8 opcode, u8 subcode,
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u32 irh_ossp, u64 ossp0,
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u64 ossp1);
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int octeon_send_soft_command(struct octeon_device *oct,
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struct octeon_soft_command *sc);
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int octeon_setup_iq(struct octeon_device *oct, int ifidx,
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int q_index, union oct_txpciq iq_no, u32 num_descs,
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void *app_ctx);
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int
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octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq,
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u32 napi_budget);
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#endif /* __OCTEON_IQ_H__ */
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