39 lines
1.3 KiB
C
39 lines
1.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2018 Intel Corporation. */
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#ifndef _I40E_XSK_H_
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#define _I40E_XSK_H_
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/* This value should match the pragma in the loop_unrolled_for
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* macro. Why 4? It is strictly empirical. It seems to be a good
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* compromise between the advantage of having simultaneous outstanding
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* reads to the DMA array that can hide each others latency and the
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* disadvantage of having a larger code path.
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*/
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#define PKTS_PER_BATCH 4
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#ifdef __clang__
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#define loop_unrolled_for _Pragma("clang loop unroll_count(4)") for
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#elif __GNUC__ >= 8
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#define loop_unrolled_for _Pragma("GCC unroll 4") for
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#else
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#define loop_unrolled_for for
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#endif
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struct i40e_vsi;
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struct xsk_buff_pool;
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int i40e_queue_pair_disable(struct i40e_vsi *vsi, int queue_pair);
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int i40e_queue_pair_enable(struct i40e_vsi *vsi, int queue_pair);
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int i40e_xsk_pool_setup(struct i40e_vsi *vsi, struct xsk_buff_pool *pool,
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u16 qid);
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bool i40e_alloc_rx_buffers_zc(struct i40e_ring *rx_ring, u16 cleaned_count);
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int i40e_clean_rx_irq_zc(struct i40e_ring *rx_ring, int budget);
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bool i40e_clean_xdp_tx_irq(struct i40e_vsi *vsi, struct i40e_ring *tx_ring);
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int i40e_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
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int i40e_realloc_rx_bi_zc(struct i40e_vsi *vsi, bool zc);
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void i40e_clear_rx_bi_zc(struct i40e_ring *rx_ring);
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#endif /* _I40E_XSK_H_ */
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