309 lines
11 KiB
C
309 lines
11 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2021, Intel Corporation. */
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#ifndef _ICE_PTP_H_
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#define _ICE_PTP_H_
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#include <linux/ptp_clock_kernel.h>
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#include <linux/kthread.h>
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#include "ice_ptp_hw.h"
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enum ice_ptp_pin_e810 {
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GPIO_20 = 0,
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GPIO_21,
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GPIO_22,
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GPIO_23,
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NUM_PTP_PIN_E810
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};
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enum ice_ptp_pin_e810t {
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GNSS = 0,
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SMA1,
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UFL1,
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SMA2,
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UFL2,
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NUM_PTP_PINS_E810T
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};
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struct ice_perout_channel {
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bool ena;
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u32 gpio_pin;
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u64 period;
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u64 start_time;
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};
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/* The ice hardware captures Tx hardware timestamps in the PHY. The timestamp
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* is stored in a buffer of registers. Depending on the specific hardware,
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* this buffer might be shared across multiple PHY ports.
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*
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* On transmit of a packet to be timestamped, software is responsible for
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* selecting an open index. Hardware makes no attempt to lock or prevent
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* re-use of an index for multiple packets.
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*
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* To handle this, timestamp indexes must be tracked by software to ensure
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* that an index is not re-used for multiple transmitted packets. The
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* structures and functions declared in this file track the available Tx
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* register indexes, as well as provide storage for the SKB pointers.
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*
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* To allow multiple ports to access the shared register block independently,
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* the blocks are split up so that indexes are assigned to each port based on
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* hardware logical port number.
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*
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* The timestamp blocks are handled differently for E810- and E822-based
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* devices. In E810 devices, each port has its own block of timestamps, while in
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* E822 there is a need to logically break the block of registers into smaller
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* chunks based on the port number to avoid collisions.
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*
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* Example for port 5 in E810:
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* +--------+--------+--------+--------+--------+--------+--------+--------+
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* |register|register|register|register|register|register|register|register|
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* | block | block | block | block | block | block | block | block |
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* | for | for | for | for | for | for | for | for |
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* | port 0 | port 1 | port 2 | port 3 | port 4 | port 5 | port 6 | port 7 |
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* +--------+--------+--------+--------+--------+--------+--------+--------+
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* ^^
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* ||
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* |--- quad offset is always 0
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* ---- quad number
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*
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* Example for port 5 in E822:
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* +-----------------------------+-----------------------------+
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* | register block for quad 0 | register block for quad 1 |
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* |+------+------+------+------+|+------+------+------+------+|
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* ||port 0|port 1|port 2|port 3|||port 0|port 1|port 2|port 3||
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* |+------+------+------+------+|+------+------+------+------+|
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* +-----------------------------+-------^---------------------+
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* ^ |
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* | --- quad offset*
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* ---- quad number
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*
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* * PHY port 5 is port 1 in quad 1
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*
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*/
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/**
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* struct ice_tx_tstamp - Tracking for a single Tx timestamp
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* @skb: pointer to the SKB for this timestamp request
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* @start: jiffies when the timestamp was first requested
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* @cached_tstamp: last read timestamp
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*
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* This structure tracks a single timestamp request. The SKB pointer is
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* provided when initiating a request. The start time is used to ensure that
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* we discard old requests that were not fulfilled within a 2 second time
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* window.
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* Timestamp values in the PHY are read only and do not get cleared except at
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* hardware reset or when a new timestamp value is captured.
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*
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* Some PHY types do not provide a "ready" bitmap indicating which timestamp
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* indexes are valid. In these cases, we use a cached_tstamp to keep track of
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* the last timestamp we read for a given index. If the current timestamp
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* value is the same as the cached value, we assume a new timestamp hasn't
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* been captured. This avoids reporting stale timestamps to the stack. This is
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* only done if the verify_cached flag is set in ice_ptp_tx structure.
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*/
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struct ice_tx_tstamp {
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struct sk_buff *skb;
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unsigned long start;
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u64 cached_tstamp;
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};
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/**
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* struct ice_ptp_tx - Tracking structure for all Tx timestamp requests on a port
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* @lock: lock to prevent concurrent access to fields of this struct
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* @tstamps: array of len to store outstanding requests
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* @in_use: bitmap of len to indicate which slots are in use
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* @stale: bitmap of len to indicate slots which have stale timestamps
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* @block: which memory block (quad or port) the timestamps are captured in
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* @offset: offset into timestamp block to get the real index
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* @len: length of the tstamps and in_use fields.
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* @init: if true, the tracker is initialized;
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* @calibrating: if true, the PHY is calibrating the Tx offset. During this
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* window, timestamps are temporarily disabled.
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* @verify_cached: if true, verify new timestamp differs from last read value
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*/
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struct ice_ptp_tx {
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spinlock_t lock; /* lock protecting in_use bitmap */
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struct ice_tx_tstamp *tstamps;
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unsigned long *in_use;
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unsigned long *stale;
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u8 block;
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u8 offset;
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u8 len;
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u8 init : 1;
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u8 calibrating : 1;
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u8 verify_cached : 1;
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};
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/* Quad and port information for initializing timestamp blocks */
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#define INDEX_PER_QUAD 64
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#define INDEX_PER_PORT_E822 16
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#define INDEX_PER_PORT_E810 64
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/**
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* struct ice_ptp_port - data used to initialize an external port for PTP
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*
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* This structure contains data indicating whether a single external port is
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* ready for PTP functionality. It is used to track the port initialization
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* and determine when the port's PHY offset is valid.
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*
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* @tx: Tx timestamp tracking for this port
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* @ov_work: delayed work task for tracking when PHY offset is valid
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* @ps_lock: mutex used to protect the overall PTP PHY start procedure
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* @link_up: indicates whether the link is up
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* @tx_fifo_busy_cnt: number of times the Tx FIFO was busy
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* @port_num: the port number this structure represents
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*/
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struct ice_ptp_port {
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struct ice_ptp_tx tx;
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struct kthread_delayed_work ov_work;
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struct mutex ps_lock; /* protects overall PTP PHY start procedure */
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bool link_up;
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u8 tx_fifo_busy_cnt;
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u8 port_num;
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};
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#define GLTSYN_TGT_H_IDX_MAX 4
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/**
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* struct ice_ptp - data used for integrating with CONFIG_PTP_1588_CLOCK
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* @port: data for the PHY port initialization procedure
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* @work: delayed work function for periodic tasks
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* @extts_work: work function for handling external Tx timestamps
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* @cached_phc_time: a cached copy of the PHC time for timestamp extension
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* @cached_phc_jiffies: jiffies when cached_phc_time was last updated
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* @ext_ts_chan: the external timestamp channel in use
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* @ext_ts_irq: the external timestamp IRQ in use
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* @kworker: kwork thread for handling periodic work
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* @perout_channels: periodic output data
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* @info: structure defining PTP hardware capabilities
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* @clock: pointer to registered PTP clock device
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* @tstamp_config: hardware timestamping configuration
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* @reset_time: kernel time after clock stop on reset
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* @tx_hwtstamp_skipped: number of Tx time stamp requests skipped
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* @tx_hwtstamp_timeouts: number of Tx skbs discarded with no time stamp
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* @tx_hwtstamp_flushed: number of Tx skbs flushed due to interface closed
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* @tx_hwtstamp_discarded: number of Tx skbs discarded due to cached PHC time
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* being too old to correctly extend timestamp
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* @late_cached_phc_updates: number of times cached PHC update is late
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*/
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struct ice_ptp {
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struct ice_ptp_port port;
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struct kthread_delayed_work work;
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struct kthread_work extts_work;
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u64 cached_phc_time;
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unsigned long cached_phc_jiffies;
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u8 ext_ts_chan;
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u8 ext_ts_irq;
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struct kthread_worker *kworker;
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struct ice_perout_channel perout_channels[GLTSYN_TGT_H_IDX_MAX];
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struct ptp_clock_info info;
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struct ptp_clock *clock;
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struct hwtstamp_config tstamp_config;
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u64 reset_time;
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u32 tx_hwtstamp_skipped;
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u32 tx_hwtstamp_timeouts;
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u32 tx_hwtstamp_flushed;
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u32 tx_hwtstamp_discarded;
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u32 late_cached_phc_updates;
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};
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#define __ptp_port_to_ptp(p) \
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container_of((p), struct ice_ptp, port)
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#define ptp_port_to_pf(p) \
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container_of(__ptp_port_to_ptp((p)), struct ice_pf, ptp)
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#define __ptp_info_to_ptp(i) \
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container_of((i), struct ice_ptp, info)
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#define ptp_info_to_pf(i) \
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container_of(__ptp_info_to_ptp((i)), struct ice_pf, ptp)
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#define PFTSYN_SEM_BYTES 4
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#define PTP_SHARED_CLK_IDX_VALID BIT(31)
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#define TS_CMD_MASK 0xF
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#define SYNC_EXEC_CMD 0x3
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#define ICE_PTP_TS_VALID BIT(0)
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#define FIFO_EMPTY BIT(2)
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#define FIFO_OK 0xFF
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#define ICE_PTP_FIFO_NUM_CHECKS 5
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/* Per-channel register definitions */
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#define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8))
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#define GLTSYN_AUX_IN(_chan, _idx) (GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8))
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#define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8))
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#define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16))
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#define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16))
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#define GLTSYN_EVNT_L(_chan, _idx) (GLTSYN_EVNT_L_0(_idx) + ((_chan) * 16))
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#define GLTSYN_EVNT_H(_chan, _idx) (GLTSYN_EVNT_H_0(_idx) + ((_chan) * 16))
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#define GLTSYN_EVNT_H_IDX_MAX 3
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/* Pin definitions for PTP PPS out */
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#define PPS_CLK_GEN_CHAN 3
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#define PPS_CLK_SRC_CHAN 2
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#define PPS_PIN_INDEX 5
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#define TIME_SYNC_PIN_INDEX 4
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#define N_EXT_TS_E810 3
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#define N_PER_OUT_E810 4
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#define N_PER_OUT_E810T 3
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#define N_PER_OUT_NO_SMA_E810T 2
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#define N_EXT_TS_NO_SMA_E810T 2
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#define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
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#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
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struct ice_pf;
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int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr);
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int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr);
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void ice_ptp_cfg_timestamp(struct ice_pf *pf, bool ena);
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int ice_get_ptp_clock_index(struct ice_pf *pf);
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s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb);
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bool ice_ptp_process_ts(struct ice_pf *pf);
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void
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ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring,
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union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb);
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void ice_ptp_reset(struct ice_pf *pf);
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void ice_ptp_prepare_for_reset(struct ice_pf *pf);
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void ice_ptp_init(struct ice_pf *pf);
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void ice_ptp_release(struct ice_pf *pf);
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void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup);
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#else /* IS_ENABLED(CONFIG_PTP_1588_CLOCK) */
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static inline int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)
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{
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return -EOPNOTSUPP;
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}
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static inline int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr)
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{
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return -EOPNOTSUPP;
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}
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static inline void ice_ptp_cfg_timestamp(struct ice_pf *pf, bool ena) { }
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static inline int ice_get_ptp_clock_index(struct ice_pf *pf)
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{
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return -1;
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}
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static inline s8
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ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)
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{
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return -1;
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}
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static inline bool ice_ptp_process_ts(struct ice_pf *pf)
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{
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return true;
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}
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static inline void
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ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring,
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union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb) { }
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static inline void ice_ptp_reset(struct ice_pf *pf) { }
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static inline void ice_ptp_prepare_for_reset(struct ice_pf *pf) { }
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static inline void ice_ptp_init(struct ice_pf *pf) { }
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static inline void ice_ptp_release(struct ice_pf *pf) { }
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static inline void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
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{
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}
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#endif /* IS_ENABLED(CONFIG_PTP_1588_CLOCK) */
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#endif /* _ICE_PTP_H_ */
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