375 lines
7.9 KiB
C
375 lines
7.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2018-2021, Intel Corporation. */
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#ifndef _ICE_PTP_CONSTS_H_
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#define _ICE_PTP_CONSTS_H_
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/* Constant definitions related to the hardware clock used for PTP 1588
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* features and functionality.
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*/
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/* Constants defined for the PTP 1588 clock hardware. */
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/* struct ice_time_ref_info_e822
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*
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* E822 hardware can use different sources as the reference for the PTP
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* hardware clock. Each clock has different characteristics such as a slightly
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* different frequency, etc.
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*
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* This lookup table defines several constants that depend on the current time
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* reference. See the struct ice_time_ref_info_e822 for information about the
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* meaning of each constant.
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*/
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const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {
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/* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
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{
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/* pll_freq */
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823437500, /* 823.4375 MHz PLL */
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/* nominal_incval */
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0x136e44fabULL,
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/* pps_delay */
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11,
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},
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/* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
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{
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/* pll_freq */
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783360000, /* 783.36 MHz */
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/* nominal_incval */
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0x146cc2177ULL,
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/* pps_delay */
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12,
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},
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/* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
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{
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/* pll_freq */
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796875000, /* 796.875 MHz */
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/* nominal_incval */
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0x141414141ULL,
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/* pps_delay */
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12,
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},
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/* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
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{
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/* pll_freq */
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816000000, /* 816 MHz */
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/* nominal_incval */
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0x139b9b9baULL,
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/* pps_delay */
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12,
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},
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/* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
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{
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/* pll_freq */
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830078125, /* 830.78125 MHz */
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/* nominal_incval */
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0x134679aceULL,
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/* pps_delay */
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11,
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},
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/* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
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{
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/* pll_freq */
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783360000, /* 783.36 MHz */
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/* nominal_incval */
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0x146cc2177ULL,
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/* pps_delay */
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12,
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},
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};
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const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
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/* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
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{
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/* refclk_pre_div */
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1,
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/* feedback_div */
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197,
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/* frac_n_div */
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2621440,
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/* post_pll_div */
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6,
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},
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/* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
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{
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/* refclk_pre_div */
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5,
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/* feedback_div */
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223,
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/* frac_n_div */
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524288,
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/* post_pll_div */
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7,
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},
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/* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
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{
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/* refclk_pre_div */
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5,
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/* feedback_div */
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223,
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/* frac_n_div */
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524288,
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/* post_pll_div */
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7,
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},
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/* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
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{
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/* refclk_pre_div */
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5,
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/* feedback_div */
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159,
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/* frac_n_div */
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1572864,
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/* post_pll_div */
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6,
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},
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/* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
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{
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/* refclk_pre_div */
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5,
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/* feedback_div */
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159,
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/* frac_n_div */
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1572864,
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/* post_pll_div */
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6,
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},
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/* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
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{
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/* refclk_pre_div */
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10,
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/* feedback_div */
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223,
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/* frac_n_div */
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524288,
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/* post_pll_div */
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7,
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},
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};
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/* struct ice_vernier_info_e822
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*
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* E822 hardware calibrates the delay of the timestamp indication from the
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* actual packet transmission or reception during the initialization of the
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* PHY. To do this, the hardware mechanism uses some conversions between the
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* various clocks within the PHY block. This table defines constants used to
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* calculate the correct conversion ratios in the PHY registers.
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*
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* Many of the values relate to the PAR/PCS clock conversion registers. For
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* these registers, a value of 0 means that the associated register is not
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* used by this link speed, and that the register should be cleared by writing
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* 0. Other values specify the clock frequency in Hz.
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*/
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const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD] = {
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/* ICE_PTP_LNK_SPD_1G */
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{
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/* tx_par_clk */
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31250000, /* 31.25 MHz */
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/* rx_par_clk */
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31250000, /* 31.25 MHz */
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/* tx_pcs_clk */
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125000000, /* 125 MHz */
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/* rx_pcs_clk */
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125000000, /* 125 MHz */
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/* tx_desk_rsgb_par */
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0, /* unused */
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/* rx_desk_rsgb_par */
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0, /* unused */
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/* tx_desk_rsgb_pcs */
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0, /* unused */
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/* rx_desk_rsgb_pcs */
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0, /* unused */
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/* tx_fixed_delay */
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25140,
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/* pmd_adj_divisor */
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10000000,
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/* rx_fixed_delay */
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17372,
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},
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/* ICE_PTP_LNK_SPD_10G */
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{
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/* tx_par_clk */
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257812500, /* 257.8125 MHz */
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/* rx_par_clk */
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257812500, /* 257.8125 MHz */
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/* tx_pcs_clk */
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156250000, /* 156.25 MHz */
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/* rx_pcs_clk */
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156250000, /* 156.25 MHz */
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/* tx_desk_rsgb_par */
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0, /* unused */
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/* rx_desk_rsgb_par */
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0, /* unused */
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/* tx_desk_rsgb_pcs */
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0, /* unused */
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/* rx_desk_rsgb_pcs */
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0, /* unused */
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/* tx_fixed_delay */
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6938,
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/* pmd_adj_divisor */
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82500000,
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/* rx_fixed_delay */
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6212,
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},
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/* ICE_PTP_LNK_SPD_25G */
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{
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/* tx_par_clk */
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644531250, /* 644.53125 MHZ */
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/* rx_par_clk */
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644531250, /* 644.53125 MHz */
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/* tx_pcs_clk */
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390625000, /* 390.625 MHz */
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/* rx_pcs_clk */
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390625000, /* 390.625 MHz */
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/* tx_desk_rsgb_par */
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0, /* unused */
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/* rx_desk_rsgb_par */
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0, /* unused */
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/* tx_desk_rsgb_pcs */
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0, /* unused */
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/* rx_desk_rsgb_pcs */
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0, /* unused */
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/* tx_fixed_delay */
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2778,
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/* pmd_adj_divisor */
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206250000,
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/* rx_fixed_delay */
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2491,
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},
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/* ICE_PTP_LNK_SPD_25G_RS */
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{
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/* tx_par_clk */
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0, /* unused */
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/* rx_par_clk */
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0, /* unused */
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/* tx_pcs_clk */
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0, /* unused */
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/* rx_pcs_clk */
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0, /* unused */
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/* tx_desk_rsgb_par */
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161132812, /* 162.1328125 MHz Reed Solomon gearbox */
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/* rx_desk_rsgb_par */
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161132812, /* 162.1328125 MHz Reed Solomon gearbox */
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/* tx_desk_rsgb_pcs */
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97656250, /* 97.62625 MHz Reed Solomon gearbox */
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/* rx_desk_rsgb_pcs */
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97656250, /* 97.62625 MHz Reed Solomon gearbox */
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/* tx_fixed_delay */
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3928,
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/* pmd_adj_divisor */
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206250000,
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/* rx_fixed_delay */
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29535,
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},
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/* ICE_PTP_LNK_SPD_40G */
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{
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/* tx_par_clk */
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257812500,
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/* rx_par_clk */
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257812500,
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/* tx_pcs_clk */
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156250000, /* 156.25 MHz */
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/* rx_pcs_clk */
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156250000, /* 156.25 MHz */
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/* tx_desk_rsgb_par */
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0, /* unused */
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/* rx_desk_rsgb_par */
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156250000, /* 156.25 MHz deskew clock */
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/* tx_desk_rsgb_pcs */
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0, /* unused */
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/* rx_desk_rsgb_pcs */
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156250000, /* 156.25 MHz deskew clock */
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/* tx_fixed_delay */
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5666,
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/* pmd_adj_divisor */
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82500000,
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/* rx_fixed_delay */
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4244,
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},
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/* ICE_PTP_LNK_SPD_50G */
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{
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/* tx_par_clk */
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644531250, /* 644.53125 MHZ */
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/* rx_par_clk */
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644531250, /* 644.53125 MHZ */
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/* tx_pcs_clk */
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390625000, /* 390.625 MHz */
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/* rx_pcs_clk */
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390625000, /* 390.625 MHz */
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/* tx_desk_rsgb_par */
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0, /* unused */
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/* rx_desk_rsgb_par */
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195312500, /* 193.3125 MHz deskew clock */
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/* tx_desk_rsgb_pcs */
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0, /* unused */
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/* rx_desk_rsgb_pcs */
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195312500, /* 193.3125 MHz deskew clock */
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/* tx_fixed_delay */
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2778,
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/* pmd_adj_divisor */
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206250000,
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/* rx_fixed_delay */
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2868,
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},
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/* ICE_PTP_LNK_SPD_50G_RS */
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{
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/* tx_par_clk */
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0, /* unused */
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/* rx_par_clk */
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644531250, /* 644.53125 MHz */
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/* tx_pcs_clk */
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0, /* unused */
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/* rx_pcs_clk */
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644531250, /* 644.53125 MHz */
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/* tx_desk_rsgb_par */
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322265625, /* 322.265625 MHz Reed Solomon gearbox */
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/* rx_desk_rsgb_par */
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322265625, /* 322.265625 MHz Reed Solomon gearbox */
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/* tx_desk_rsgb_pcs */
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644531250, /* 644.53125 MHz Reed Solomon gearbox */
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/* rx_desk_rsgb_pcs */
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644531250, /* 644.53125 MHz Reed Solomon gearbox */
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/* tx_fixed_delay */
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2095,
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/* pmd_adj_divisor */
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206250000,
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/* rx_fixed_delay */
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14524,
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},
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/* ICE_PTP_LNK_SPD_100G_RS */
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{
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/* tx_par_clk */
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0, /* unused */
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/* rx_par_clk */
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644531250, /* 644.53125 MHz */
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/* tx_pcs_clk */
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0, /* unused */
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/* rx_pcs_clk */
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644531250, /* 644.53125 MHz */
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/* tx_desk_rsgb_par */
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644531250, /* 644.53125 MHz Reed Solomon gearbox */
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/* rx_desk_rsgb_par */
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644531250, /* 644.53125 MHz Reed Solomon gearbox */
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/* tx_desk_rsgb_pcs */
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644531250, /* 644.53125 MHz Reed Solomon gearbox */
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/* rx_desk_rsgb_pcs */
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644531250, /* 644.53125 MHz Reed Solomon gearbox */
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/* tx_fixed_delay */
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1620,
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/* pmd_adj_divisor */
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206250000,
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/* rx_fixed_delay */
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7775,
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},
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};
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#endif /* _ICE_PTP_CONSTS_H_ */
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