484 lines
14 KiB
C
484 lines
14 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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#ifndef _ICE_TXRX_H_
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#define _ICE_TXRX_H_
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#include "ice_type.h"
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#define ICE_DFLT_IRQ_WORK 256
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#define ICE_RXBUF_3072 3072
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#define ICE_RXBUF_2048 2048
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#define ICE_RXBUF_1664 1664
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#define ICE_RXBUF_1536 1536
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#define ICE_MAX_CHAINED_RX_BUFS 5
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#define ICE_MAX_BUF_TXD 8
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#define ICE_MIN_TX_LEN 17
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#define ICE_MAX_FRAME_LEGACY_RX 8320
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/* The size limit for a transmit buffer in a descriptor is (16K - 1).
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* In order to align with the read requests we will align the value to
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* the nearest 4K which represents our maximum read request size.
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*/
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#define ICE_MAX_READ_REQ_SIZE 4096
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#define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1)
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#define ICE_MAX_DATA_PER_TXD_ALIGNED \
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(~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD)
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#define ICE_MAX_TXQ_PER_TXQG 128
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/* Attempt to maximize the headroom available for incoming frames. We use a 2K
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* buffer for MTUs <= 1500 and need 1536/1534 to store the data for the frame.
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* This leaves us with 512 bytes of room. From that we need to deduct the
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* space needed for the shared info and the padding needed to IP align the
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* frame.
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*
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* Note: For cache line sizes 256 or larger this value is going to end
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* up negative. In these cases we should fall back to the legacy
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* receive path.
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*/
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#if (PAGE_SIZE < 8192)
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#define ICE_2K_TOO_SMALL_WITH_PADDING \
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((unsigned int)(NET_SKB_PAD + ICE_RXBUF_1536) > \
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SKB_WITH_OVERHEAD(ICE_RXBUF_2048))
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/**
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* ice_compute_pad - compute the padding
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* @rx_buf_len: buffer length
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*
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* Figure out the size of half page based on given buffer length and
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* then subtract the skb_shared_info followed by subtraction of the
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* actual buffer length; this in turn results in the actual space that
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* is left for padding usage
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*/
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static inline int ice_compute_pad(int rx_buf_len)
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{
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int half_page_size;
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half_page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
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return SKB_WITH_OVERHEAD(half_page_size) - rx_buf_len;
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}
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/**
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* ice_skb_pad - determine the padding that we can supply
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*
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* Figure out the right Rx buffer size and based on that calculate the
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* padding
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*/
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static inline int ice_skb_pad(void)
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{
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int rx_buf_len;
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/* If a 2K buffer cannot handle a standard Ethernet frame then
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* optimize padding for a 3K buffer instead of a 1.5K buffer.
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*
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* For a 3K buffer we need to add enough padding to allow for
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* tailroom due to NET_IP_ALIGN possibly shifting us out of
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* cache-line alignment.
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*/
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if (ICE_2K_TOO_SMALL_WITH_PADDING)
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rx_buf_len = ICE_RXBUF_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN);
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else
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rx_buf_len = ICE_RXBUF_1536;
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/* if needed make room for NET_IP_ALIGN */
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rx_buf_len -= NET_IP_ALIGN;
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return ice_compute_pad(rx_buf_len);
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}
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#define ICE_SKB_PAD ice_skb_pad()
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#else
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#define ICE_2K_TOO_SMALL_WITH_PADDING false
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#define ICE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
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#endif
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/* We are assuming that the cache line is always 64 Bytes here for ice.
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* In order to make sure that is a correct assumption there is a check in probe
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* to print a warning if the read from GLPCI_CNF2 tells us that the cache line
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* size is 128 bytes. We do it this way because we do not want to read the
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* GLPCI_CNF2 register or a variable containing the value on every pass through
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* the Tx path.
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*/
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#define ICE_CACHE_LINE_BYTES 64
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#define ICE_DESCS_PER_CACHE_LINE (ICE_CACHE_LINE_BYTES / \
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sizeof(struct ice_tx_desc))
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#define ICE_DESCS_FOR_CTX_DESC 1
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#define ICE_DESCS_FOR_SKB_DATA_PTR 1
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/* Tx descriptors needed, worst case */
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#define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \
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ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR)
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#define ICE_DESC_UNUSED(R) \
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(u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
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(R)->next_to_clean - (R)->next_to_use - 1)
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#define ICE_RX_DESC_UNUSED(R) \
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((((R)->first_desc > (R)->next_to_use) ? 0 : (R)->count) + \
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(R)->first_desc - (R)->next_to_use - 1)
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#define ICE_RING_QUARTER(R) ((R)->count >> 2)
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#define ICE_TX_FLAGS_TSO BIT(0)
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#define ICE_TX_FLAGS_HW_VLAN BIT(1)
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#define ICE_TX_FLAGS_SW_VLAN BIT(2)
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/* Free, was ICE_TX_FLAGS_DUMMY_PKT */
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#define ICE_TX_FLAGS_TSYN BIT(4)
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#define ICE_TX_FLAGS_IPV4 BIT(5)
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#define ICE_TX_FLAGS_IPV6 BIT(6)
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#define ICE_TX_FLAGS_TUNNEL BIT(7)
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#define ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN BIT(8)
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#define ICE_XDP_PASS 0
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#define ICE_XDP_CONSUMED BIT(0)
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#define ICE_XDP_TX BIT(1)
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#define ICE_XDP_REDIR BIT(2)
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#define ICE_XDP_EXIT BIT(3)
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#define ICE_SKB_CONSUMED ICE_XDP_CONSUMED
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#define ICE_RX_DMA_ATTR \
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(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
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#define ICE_ETH_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
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#define ICE_TXD_LAST_DESC_CMD (ICE_TX_DESC_CMD_EOP | ICE_TX_DESC_CMD_RS)
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/**
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* enum ice_tx_buf_type - type of &ice_tx_buf to act on Tx completion
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* @ICE_TX_BUF_EMPTY: unused OR XSk frame, no action required
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* @ICE_TX_BUF_DUMMY: dummy Flow Director packet, unmap and kfree()
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* @ICE_TX_BUF_FRAG: mapped skb OR &xdp_buff frag, only unmap DMA
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* @ICE_TX_BUF_SKB: &sk_buff, unmap and consume_skb(), update stats
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* @ICE_TX_BUF_XDP_TX: &xdp_buff, unmap and page_frag_free(), stats
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* @ICE_TX_BUF_XDP_XMIT: &xdp_frame, unmap and xdp_return_frame(), stats
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* @ICE_TX_BUF_XSK_TX: &xdp_buff on XSk queue, xsk_buff_free(), stats
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*/
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enum ice_tx_buf_type {
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ICE_TX_BUF_EMPTY = 0U,
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ICE_TX_BUF_DUMMY,
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ICE_TX_BUF_FRAG,
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ICE_TX_BUF_SKB,
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ICE_TX_BUF_XDP_TX,
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ICE_TX_BUF_XDP_XMIT,
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ICE_TX_BUF_XSK_TX,
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};
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struct ice_tx_buf {
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union {
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struct ice_tx_desc *next_to_watch;
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u32 rs_idx;
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};
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union {
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void *raw_buf; /* used for XDP_TX and FDir rules */
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struct sk_buff *skb; /* used for .ndo_start_xmit() */
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struct xdp_frame *xdpf; /* used for .ndo_xdp_xmit() */
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struct xdp_buff *xdp; /* used for XDP_TX ZC */
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};
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unsigned int bytecount;
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union {
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unsigned int gso_segs;
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unsigned int nr_frags; /* used for mbuf XDP */
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};
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u32 tx_flags:12;
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u32 type:4; /* &ice_tx_buf_type */
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u32 vid:16;
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DEFINE_DMA_UNMAP_LEN(len);
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DEFINE_DMA_UNMAP_ADDR(dma);
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};
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struct ice_tx_offload_params {
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u64 cd_qw1;
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struct ice_tx_ring *tx_ring;
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u32 td_cmd;
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u32 td_offset;
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u32 td_l2tag1;
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u32 cd_tunnel_params;
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u16 cd_l2tag2;
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u8 header_len;
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};
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struct ice_rx_buf {
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dma_addr_t dma;
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struct page *page;
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unsigned int page_offset;
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unsigned int pgcnt;
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unsigned int act;
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unsigned int pagecnt_bias;
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};
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struct ice_q_stats {
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u64 pkts;
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u64 bytes;
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};
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struct ice_txq_stats {
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u64 restart_q;
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u64 tx_busy;
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u64 tx_linearize;
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int prev_pkt; /* negative if no pending Tx descriptors */
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};
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struct ice_rxq_stats {
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u64 non_eop_descs;
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u64 alloc_page_failed;
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u64 alloc_buf_failed;
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};
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struct ice_ring_stats {
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struct rcu_head rcu; /* to avoid race on free */
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struct ice_q_stats stats;
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struct u64_stats_sync syncp;
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union {
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struct ice_txq_stats tx_stats;
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struct ice_rxq_stats rx_stats;
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};
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};
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enum ice_ring_state_t {
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ICE_TX_XPS_INIT_DONE,
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ICE_TX_NBITS,
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};
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/* this enum matches hardware bits and is meant to be used by DYN_CTLN
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* registers and QINT registers or more generally anywhere in the manual
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* mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
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* register but instead is a special value meaning "don't update" ITR0/1/2.
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*/
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enum ice_dyn_idx_t {
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ICE_IDX_ITR0 = 0,
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ICE_IDX_ITR1 = 1,
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ICE_IDX_ITR2 = 2,
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ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
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};
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/* Header split modes defined by DTYPE field of Rx RLAN context */
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enum ice_rx_dtype {
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ICE_RX_DTYPE_NO_SPLIT = 0,
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ICE_RX_DTYPE_HEADER_SPLIT = 1,
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ICE_RX_DTYPE_SPLIT_ALWAYS = 2,
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};
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/* indices into GLINT_ITR registers */
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#define ICE_RX_ITR ICE_IDX_ITR0
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#define ICE_TX_ITR ICE_IDX_ITR1
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#define ICE_ITR_8K 124
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#define ICE_ITR_20K 50
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#define ICE_ITR_MAX 8160 /* 0x1FE0 */
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#define ICE_DFLT_TX_ITR ICE_ITR_20K
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#define ICE_DFLT_RX_ITR ICE_ITR_20K
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enum ice_dynamic_itr {
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ITR_STATIC = 0,
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ITR_DYNAMIC = 1
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};
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#define ITR_IS_DYNAMIC(rc) ((rc)->itr_mode == ITR_DYNAMIC)
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#define ICE_ITR_GRAN_S 1 /* ITR granularity is always 2us */
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#define ICE_ITR_GRAN_US BIT(ICE_ITR_GRAN_S)
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#define ICE_ITR_MASK 0x1FFE /* ITR register value alignment mask */
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#define ITR_REG_ALIGN(setting) ((setting) & ICE_ITR_MASK)
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#define ICE_DFLT_INTRL 0
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#define ICE_MAX_INTRL 236
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#define ICE_IN_WB_ON_ITR_MODE 255
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/* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows
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* setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also,
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* set the write-back latency to the usecs passed in.
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*/
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#define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx) \
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((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \
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GLINT_DYN_CTL_INTERVAL_M) | \
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(((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \
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GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \
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GLINT_DYN_CTL_WB_ON_ITR_M)
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/* Legacy or Advanced Mode Queue */
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#define ICE_TX_ADVANCED 0
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#define ICE_TX_LEGACY 1
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/* descriptor ring, associated with a VSI */
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struct ice_rx_ring {
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/* CL1 - 1st cacheline starts here */
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struct ice_rx_ring *next; /* pointer to next ring in q_vector */
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void *desc; /* Descriptor ring memory */
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struct device *dev; /* Used for DMA mapping */
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struct net_device *netdev; /* netdev ring maps to */
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struct ice_vsi *vsi; /* Backreference to associated VSI */
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struct ice_q_vector *q_vector; /* Backreference to associated vector */
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u8 __iomem *tail;
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u16 q_index; /* Queue number of ring */
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u16 count; /* Number of descriptors */
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u16 reg_idx; /* HW register index of the ring */
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u16 next_to_alloc;
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/* CL2 - 2nd cacheline starts here */
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union {
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struct ice_rx_buf *rx_buf;
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struct xdp_buff **xdp_buf;
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};
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struct xdp_buff xdp;
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/* CL3 - 3rd cacheline starts here */
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struct bpf_prog *xdp_prog;
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u16 rx_offset;
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/* used in interrupt processing */
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u16 next_to_use;
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u16 next_to_clean;
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u16 first_desc;
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/* stats structs */
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struct ice_ring_stats *ring_stats;
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struct rcu_head rcu; /* to avoid race on free */
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/* CL4 - 4th cacheline starts here */
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struct ice_channel *ch;
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struct ice_tx_ring *xdp_ring;
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struct xsk_buff_pool *xsk_pool;
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dma_addr_t dma; /* physical address of ring */
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u64 cached_phctime;
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u16 rx_buf_len;
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|
|
u8 dcb_tc; /* Traffic class of ring */
|
||
|
|
u8 ptp_rx;
|
||
|
|
#define ICE_RX_FLAGS_RING_BUILD_SKB BIT(1)
|
||
|
|
#define ICE_RX_FLAGS_CRC_STRIP_DIS BIT(2)
|
||
|
|
u8 flags;
|
||
|
|
/* CL5 - 5th cacheline starts here */
|
||
|
|
struct xdp_rxq_info xdp_rxq;
|
||
|
|
} ____cacheline_internodealigned_in_smp;
|
||
|
|
|
||
|
|
struct ice_tx_ring {
|
||
|
|
/* CL1 - 1st cacheline starts here */
|
||
|
|
struct ice_tx_ring *next; /* pointer to next ring in q_vector */
|
||
|
|
void *desc; /* Descriptor ring memory */
|
||
|
|
struct device *dev; /* Used for DMA mapping */
|
||
|
|
u8 __iomem *tail;
|
||
|
|
struct ice_tx_buf *tx_buf;
|
||
|
|
struct ice_q_vector *q_vector; /* Backreference to associated vector */
|
||
|
|
struct net_device *netdev; /* netdev ring maps to */
|
||
|
|
struct ice_vsi *vsi; /* Backreference to associated VSI */
|
||
|
|
/* CL2 - 2nd cacheline starts here */
|
||
|
|
dma_addr_t dma; /* physical address of ring */
|
||
|
|
struct xsk_buff_pool *xsk_pool;
|
||
|
|
u16 next_to_use;
|
||
|
|
u16 next_to_clean;
|
||
|
|
u16 q_handle; /* Queue handle per TC */
|
||
|
|
u16 reg_idx; /* HW register index of the ring */
|
||
|
|
u16 count; /* Number of descriptors */
|
||
|
|
u16 q_index; /* Queue number of ring */
|
||
|
|
u16 xdp_tx_active;
|
||
|
|
/* stats structs */
|
||
|
|
struct ice_ring_stats *ring_stats;
|
||
|
|
/* CL3 - 3rd cacheline starts here */
|
||
|
|
struct rcu_head rcu; /* to avoid race on free */
|
||
|
|
DECLARE_BITMAP(xps_state, ICE_TX_NBITS); /* XPS Config State */
|
||
|
|
struct ice_channel *ch;
|
||
|
|
struct ice_ptp_tx *tx_tstamps;
|
||
|
|
spinlock_t tx_lock;
|
||
|
|
u32 txq_teid; /* Added Tx queue TEID */
|
||
|
|
/* CL4 - 4th cacheline starts here */
|
||
|
|
#define ICE_TX_FLAGS_RING_XDP BIT(0)
|
||
|
|
#define ICE_TX_FLAGS_RING_VLAN_L2TAG1 BIT(1)
|
||
|
|
#define ICE_TX_FLAGS_RING_VLAN_L2TAG2 BIT(2)
|
||
|
|
u8 flags;
|
||
|
|
u8 dcb_tc; /* Traffic class of ring */
|
||
|
|
u8 ptp_tx;
|
||
|
|
} ____cacheline_internodealigned_in_smp;
|
||
|
|
|
||
|
|
static inline bool ice_ring_uses_build_skb(struct ice_rx_ring *ring)
|
||
|
|
{
|
||
|
|
return !!(ring->flags & ICE_RX_FLAGS_RING_BUILD_SKB);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void ice_set_ring_build_skb_ena(struct ice_rx_ring *ring)
|
||
|
|
{
|
||
|
|
ring->flags |= ICE_RX_FLAGS_RING_BUILD_SKB;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void ice_clear_ring_build_skb_ena(struct ice_rx_ring *ring)
|
||
|
|
{
|
||
|
|
ring->flags &= ~ICE_RX_FLAGS_RING_BUILD_SKB;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool ice_ring_ch_enabled(struct ice_tx_ring *ring)
|
||
|
|
{
|
||
|
|
return !!ring->ch;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool ice_ring_is_xdp(struct ice_tx_ring *ring)
|
||
|
|
{
|
||
|
|
return !!(ring->flags & ICE_TX_FLAGS_RING_XDP);
|
||
|
|
}
|
||
|
|
|
||
|
|
enum ice_container_type {
|
||
|
|
ICE_RX_CONTAINER,
|
||
|
|
ICE_TX_CONTAINER,
|
||
|
|
};
|
||
|
|
|
||
|
|
struct ice_ring_container {
|
||
|
|
/* head of linked-list of rings */
|
||
|
|
union {
|
||
|
|
struct ice_rx_ring *rx_ring;
|
||
|
|
struct ice_tx_ring *tx_ring;
|
||
|
|
};
|
||
|
|
struct dim dim; /* data for net_dim algorithm */
|
||
|
|
u16 itr_idx; /* index in the interrupt vector */
|
||
|
|
/* this matches the maximum number of ITR bits, but in usec
|
||
|
|
* values, so it is shifted left one bit (bit zero is ignored)
|
||
|
|
*/
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
u16 itr_setting:13;
|
||
|
|
u16 itr_reserved:2;
|
||
|
|
u16 itr_mode:1;
|
||
|
|
};
|
||
|
|
u16 itr_settings;
|
||
|
|
};
|
||
|
|
enum ice_container_type type;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct ice_coalesce_stored {
|
||
|
|
u16 itr_tx;
|
||
|
|
u16 itr_rx;
|
||
|
|
u8 intrl;
|
||
|
|
u8 tx_valid;
|
||
|
|
u8 rx_valid;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* iterator for handling rings in ring container */
|
||
|
|
#define ice_for_each_rx_ring(pos, head) \
|
||
|
|
for (pos = (head).rx_ring; pos; pos = pos->next)
|
||
|
|
|
||
|
|
#define ice_for_each_tx_ring(pos, head) \
|
||
|
|
for (pos = (head).tx_ring; pos; pos = pos->next)
|
||
|
|
|
||
|
|
static inline unsigned int ice_rx_pg_order(struct ice_rx_ring *ring)
|
||
|
|
{
|
||
|
|
#if (PAGE_SIZE < 8192)
|
||
|
|
if (ring->rx_buf_len > (PAGE_SIZE / 2))
|
||
|
|
return 1;
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
#define ice_rx_pg_size(_ring) (PAGE_SIZE << ice_rx_pg_order(_ring))
|
||
|
|
|
||
|
|
union ice_32b_rx_flex_desc;
|
||
|
|
|
||
|
|
bool ice_alloc_rx_bufs(struct ice_rx_ring *rxr, unsigned int cleaned_count);
|
||
|
|
netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev);
|
||
|
|
u16
|
||
|
|
ice_select_queue(struct net_device *dev, struct sk_buff *skb,
|
||
|
|
struct net_device *sb_dev);
|
||
|
|
void ice_clean_tx_ring(struct ice_tx_ring *tx_ring);
|
||
|
|
void ice_clean_rx_ring(struct ice_rx_ring *rx_ring);
|
||
|
|
int ice_setup_tx_ring(struct ice_tx_ring *tx_ring);
|
||
|
|
int ice_setup_rx_ring(struct ice_rx_ring *rx_ring);
|
||
|
|
void ice_free_tx_ring(struct ice_tx_ring *tx_ring);
|
||
|
|
void ice_free_rx_ring(struct ice_rx_ring *rx_ring);
|
||
|
|
int ice_napi_poll(struct napi_struct *napi, int budget);
|
||
|
|
int
|
||
|
|
ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc,
|
||
|
|
u8 *raw_packet);
|
||
|
|
int ice_clean_rx_irq(struct ice_rx_ring *rx_ring, int budget);
|
||
|
|
void ice_clean_ctrl_tx_irq(struct ice_tx_ring *tx_ring);
|
||
|
|
#endif /* _ICE_TXRX_H_ */
|