235 lines
5.7 KiB
C
235 lines
5.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell RVU Admin Function driver
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*
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* Copyright (C) 2018 Marvell.
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*/
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#ifndef COMMON_H
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#define COMMON_H
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#include "rvu_struct.h"
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#define OTX2_ALIGN 128 /* Align to cacheline */
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#define Q_SIZE_16 0ULL /* 16 entries */
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#define Q_SIZE_64 1ULL /* 64 entries */
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#define Q_SIZE_256 2ULL
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#define Q_SIZE_1K 3ULL
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#define Q_SIZE_4K 4ULL
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#define Q_SIZE_16K 5ULL
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#define Q_SIZE_64K 6ULL
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#define Q_SIZE_256K 7ULL
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#define Q_SIZE_1M 8ULL /* Million entries */
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#define Q_SIZE_MIN Q_SIZE_16
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#define Q_SIZE_MAX Q_SIZE_1M
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#define Q_COUNT(x) (16ULL << (2 * x))
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#define Q_SIZE(x, n) ((ilog2(x) - (n)) / 2)
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/* Admin queue info */
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/* Since we intend to add only one instruction at a time,
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* keep queue size to it's minimum.
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*/
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#define AQ_SIZE Q_SIZE_16
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/* HW head & tail pointer mask */
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#define AQ_PTR_MASK 0xFFFFF
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struct qmem {
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void *base;
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dma_addr_t iova;
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int alloc_sz;
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u16 entry_sz;
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u8 align;
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u32 qsize;
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};
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static inline int qmem_alloc(struct device *dev, struct qmem **q,
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int qsize, int entry_sz)
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{
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struct qmem *qmem;
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int aligned_addr;
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if (!qsize)
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return -EINVAL;
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*q = devm_kzalloc(dev, sizeof(*qmem), GFP_KERNEL);
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if (!*q)
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return -ENOMEM;
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qmem = *q;
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qmem->entry_sz = entry_sz;
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qmem->alloc_sz = (qsize * entry_sz) + OTX2_ALIGN;
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qmem->base = dma_alloc_attrs(dev, qmem->alloc_sz, &qmem->iova,
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GFP_KERNEL, DMA_ATTR_FORCE_CONTIGUOUS);
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if (!qmem->base)
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return -ENOMEM;
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qmem->qsize = qsize;
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aligned_addr = ALIGN((u64)qmem->iova, OTX2_ALIGN);
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qmem->align = (aligned_addr - qmem->iova);
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qmem->base += qmem->align;
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qmem->iova += qmem->align;
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return 0;
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}
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static inline void qmem_free(struct device *dev, struct qmem *qmem)
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{
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if (!qmem)
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return;
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if (qmem->base)
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dma_free_attrs(dev, qmem->alloc_sz,
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qmem->base - qmem->align,
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qmem->iova - qmem->align,
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DMA_ATTR_FORCE_CONTIGUOUS);
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devm_kfree(dev, qmem);
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}
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struct admin_queue {
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struct qmem *inst;
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struct qmem *res;
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spinlock_t lock; /* Serialize inst enqueue from PFs */
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};
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/* NPA aura count */
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enum npa_aura_sz {
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NPA_AURA_SZ_0,
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NPA_AURA_SZ_128,
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NPA_AURA_SZ_256,
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NPA_AURA_SZ_512,
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NPA_AURA_SZ_1K,
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NPA_AURA_SZ_2K,
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NPA_AURA_SZ_4K,
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NPA_AURA_SZ_8K,
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NPA_AURA_SZ_16K,
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NPA_AURA_SZ_32K,
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NPA_AURA_SZ_64K,
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NPA_AURA_SZ_128K,
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NPA_AURA_SZ_256K,
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NPA_AURA_SZ_512K,
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NPA_AURA_SZ_1M,
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NPA_AURA_SZ_MAX,
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};
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#define NPA_AURA_COUNT(x) (1ULL << ((x) + 6))
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/* NPA AQ result structure for init/read/write of aura HW contexts */
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struct npa_aq_aura_res {
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struct npa_aq_res_s res;
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struct npa_aura_s aura_ctx;
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struct npa_aura_s ctx_mask;
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};
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/* NPA AQ result structure for init/read/write of pool HW contexts */
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struct npa_aq_pool_res {
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struct npa_aq_res_s res;
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struct npa_pool_s pool_ctx;
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struct npa_pool_s ctx_mask;
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};
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/* NIX Transmit schedulers */
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enum nix_scheduler {
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NIX_TXSCH_LVL_SMQ = 0x0,
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NIX_TXSCH_LVL_MDQ = 0x0,
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NIX_TXSCH_LVL_TL4 = 0x1,
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NIX_TXSCH_LVL_TL3 = 0x2,
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NIX_TXSCH_LVL_TL2 = 0x3,
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NIX_TXSCH_LVL_TL1 = 0x4,
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NIX_TXSCH_LVL_CNT = 0x5,
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};
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#define TXSCH_RR_QTM_MAX ((1 << 24) - 1)
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#define TXSCH_TL1_DFLT_RR_QTM TXSCH_RR_QTM_MAX
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#define TXSCH_TL1_DFLT_RR_PRIO (0x1ull)
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#define CN10K_MAX_DWRR_WEIGHT 16384 /* Weight is 14bit on CN10K */
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/* Min/Max packet sizes, excluding FCS */
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#define NIC_HW_MIN_FRS 40
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#define NIC_HW_MAX_FRS 9212
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#define SDP_HW_MAX_FRS 65535
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#define CN10K_LMAC_LINK_MAX_FRS 16380 /* 16k - FCS */
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#define CN10K_LBK_LINK_MAX_FRS 65535 /* 64k */
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/* NIX RX action operation*/
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#define NIX_RX_ACTIONOP_DROP (0x0ull)
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#define NIX_RX_ACTIONOP_UCAST (0x1ull)
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#define NIX_RX_ACTIONOP_UCAST_IPSEC (0x2ull)
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#define NIX_RX_ACTIONOP_MCAST (0x3ull)
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#define NIX_RX_ACTIONOP_RSS (0x4ull)
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/* Use the RX action set in the default unicast entry */
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#define NIX_RX_ACTION_DEFAULT (0xfull)
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/* NIX TX action operation*/
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#define NIX_TX_ACTIONOP_DROP (0x0ull)
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#define NIX_TX_ACTIONOP_UCAST_DEFAULT (0x1ull)
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#define NIX_TX_ACTIONOP_UCAST_CHAN (0x2ull)
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#define NIX_TX_ACTIONOP_MCAST (0x3ull)
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#define NIX_TX_ACTIONOP_DROP_VIOL (0x5ull)
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#define NPC_MCAM_KEY_X1 0
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#define NPC_MCAM_KEY_X2 1
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#define NPC_MCAM_KEY_X4 2
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#define NIX_INTFX_RX(a) (0x0ull | (a) << 1)
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#define NIX_INTFX_TX(a) (0x1ull | (a) << 1)
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/* Default interfaces are NIX0_RX and NIX0_TX */
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#define NIX_INTF_RX NIX_INTFX_RX(0)
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#define NIX_INTF_TX NIX_INTFX_TX(0)
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#define NIX_INTF_TYPE_CGX 0
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#define NIX_INTF_TYPE_LBK 1
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#define NIX_INTF_TYPE_SDP 2
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#define MAX_LMAC_PKIND 12
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#define NIX_LINK_CGX_LMAC(a, b) (0 + 4 * (a) + (b))
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#define NIX_LINK_LBK(a) (12 + (a))
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#define NIX_CHAN_CGX_LMAC_CHX(a, b, c) (0x800 + 0x100 * (a) + 0x10 * (b) + (c))
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#define NIX_CHAN_LBK_CHX(a, b) (0 + 0x100 * (a) + (b))
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#define NIX_CHAN_SDP_CH_START (0x700ull)
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#define NIX_CHAN_SDP_CHX(a) (NIX_CHAN_SDP_CH_START + (a))
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#define NIX_CHAN_SDP_NUM_CHANS 256
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#define NIX_CHAN_CPT_CH_START (0x800ull)
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/* The mask is to extract lower 10-bits of channel number
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* which CPT will pass to X2P.
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*/
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#define NIX_CHAN_CPT_X2P_MASK (0x3ffull)
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/* NIX LSO format indices.
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* As of now TSO is the only one using, so statically assigning indices.
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*/
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#define NIX_LSO_FORMAT_IDX_TSOV4 0
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#define NIX_LSO_FORMAT_IDX_TSOV6 1
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/* RSS info */
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#define MAX_RSS_GROUPS 8
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/* Group 0 has to be used in default pkt forwarding MCAM entries
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* reserved for NIXLFs. Groups 1-7 can be used for RSS for ntuple
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* filters.
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*/
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#define DEFAULT_RSS_CONTEXT_GROUP 0
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#define MAX_RSS_INDIR_TBL_SIZE 256 /* 1 << Max adder bits */
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/* NDC info */
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enum ndc_idx_e {
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NIX0_RX = 0x0,
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NIX0_TX = 0x1,
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NPA0_U = 0x2,
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NIX1_RX = 0x4,
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NIX1_TX = 0x5,
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};
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enum ndc_ctype_e {
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CACHING = 0x0,
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BYPASS = 0x1,
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};
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#define NDC_MAX_PORT 6
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#define NDC_READ_TRANS 0
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#define NDC_WRITE_TRANS 1
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#endif /* COMMON_H */
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