345 lines
9.7 KiB
C
345 lines
9.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
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/* MDIO support for Mellanox Gigabit Ethernet driver
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*
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* Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
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*/
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#include <linux/acpi.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/irqreturn.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include "mlxbf_gige.h"
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#include "mlxbf_gige_regs.h"
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#include "mlxbf_gige_mdio_bf2.h"
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#include "mlxbf_gige_mdio_bf3.h"
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static struct mlxbf_gige_mdio_gw mlxbf_gige_mdio_gw_t[] = {
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[MLXBF_GIGE_VERSION_BF2] = {
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.gw_address = MLXBF2_GIGE_MDIO_GW_OFFSET,
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.read_data_address = MLXBF2_GIGE_MDIO_GW_OFFSET,
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.busy = {
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.mask = MLXBF2_GIGE_MDIO_GW_BUSY_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_BUSY_SHIFT,
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},
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.read_data = {
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.mask = MLXBF2_GIGE_MDIO_GW_AD_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_AD_SHIFT,
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},
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.write_data = {
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.mask = MLXBF2_GIGE_MDIO_GW_AD_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_AD_SHIFT,
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},
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.devad = {
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.mask = MLXBF2_GIGE_MDIO_GW_DEVAD_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_DEVAD_SHIFT,
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},
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.partad = {
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.mask = MLXBF2_GIGE_MDIO_GW_PARTAD_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_PARTAD_SHIFT,
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},
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.opcode = {
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.mask = MLXBF2_GIGE_MDIO_GW_OPCODE_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_OPCODE_SHIFT,
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},
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.st1 = {
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.mask = MLXBF2_GIGE_MDIO_GW_ST1_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_ST1_SHIFT,
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},
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},
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[MLXBF_GIGE_VERSION_BF3] = {
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.gw_address = MLXBF3_GIGE_MDIO_GW_OFFSET,
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.read_data_address = MLXBF3_GIGE_MDIO_DATA_READ,
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.busy = {
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.mask = MLXBF3_GIGE_MDIO_GW_BUSY_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_BUSY_SHIFT,
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},
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.read_data = {
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.mask = MLXBF3_GIGE_MDIO_GW_DATA_READ_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_DATA_READ_SHIFT,
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},
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.write_data = {
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.mask = MLXBF3_GIGE_MDIO_GW_DATA_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_DATA_SHIFT,
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},
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.devad = {
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.mask = MLXBF3_GIGE_MDIO_GW_DEVAD_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_DEVAD_SHIFT,
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},
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.partad = {
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.mask = MLXBF3_GIGE_MDIO_GW_PARTAD_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_PARTAD_SHIFT,
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},
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.opcode = {
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.mask = MLXBF3_GIGE_MDIO_GW_OPCODE_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_OPCODE_SHIFT,
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},
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.st1 = {
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.mask = MLXBF3_GIGE_MDIO_GW_ST1_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_ST1_SHIFT,
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},
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},
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};
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#define MLXBF_GIGE_MDIO_FREQ_REFERENCE 156250000ULL
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#define MLXBF_GIGE_MDIO_COREPLL_CONST 16384ULL
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#define MLXBF_GIGE_MDC_CLK_NS 400
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#define MLXBF_GIGE_MDIO_PLL_I1CLK_REG1 0x4
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#define MLXBF_GIGE_MDIO_PLL_I1CLK_REG2 0x8
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#define MLXBF_GIGE_MDIO_CORE_F_SHIFT 0
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#define MLXBF_GIGE_MDIO_CORE_F_MASK GENMASK(25, 0)
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#define MLXBF_GIGE_MDIO_CORE_R_SHIFT 26
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#define MLXBF_GIGE_MDIO_CORE_R_MASK GENMASK(31, 26)
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#define MLXBF_GIGE_MDIO_CORE_OD_SHIFT 0
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#define MLXBF_GIGE_MDIO_CORE_OD_MASK GENMASK(3, 0)
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/* Support clause 22 */
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#define MLXBF_GIGE_MDIO_CL22_ST1 0x1
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#define MLXBF_GIGE_MDIO_CL22_WRITE 0x1
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#define MLXBF_GIGE_MDIO_CL22_READ 0x2
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/* Busy bit is set by software and cleared by hardware */
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#define MLXBF_GIGE_MDIO_SET_BUSY 0x1
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#define MLXBF_GIGE_BF2_COREPLL_ADDR 0x02800c30
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#define MLXBF_GIGE_BF2_COREPLL_SIZE 0x0000000c
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#define MLXBF_GIGE_BF3_COREPLL_ADDR 0x13409824
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#define MLXBF_GIGE_BF3_COREPLL_SIZE 0x00000010
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static struct resource corepll_params[] = {
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[MLXBF_GIGE_VERSION_BF2] = {
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.start = MLXBF_GIGE_BF2_COREPLL_ADDR,
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.end = MLXBF_GIGE_BF2_COREPLL_ADDR + MLXBF_GIGE_BF2_COREPLL_SIZE - 1,
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.name = "COREPLL_RES"
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},
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[MLXBF_GIGE_VERSION_BF3] = {
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.start = MLXBF_GIGE_BF3_COREPLL_ADDR,
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.end = MLXBF_GIGE_BF3_COREPLL_ADDR + MLXBF_GIGE_BF3_COREPLL_SIZE - 1,
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.name = "COREPLL_RES"
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}
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};
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/* Returns core clock i1clk in Hz */
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static u64 calculate_i1clk(struct mlxbf_gige *priv)
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{
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u8 core_od, core_r;
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u64 freq_output;
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u32 reg1, reg2;
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u32 core_f;
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reg1 = readl(priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG1);
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reg2 = readl(priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG2);
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core_f = (reg1 & MLXBF_GIGE_MDIO_CORE_F_MASK) >>
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MLXBF_GIGE_MDIO_CORE_F_SHIFT;
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core_r = (reg1 & MLXBF_GIGE_MDIO_CORE_R_MASK) >>
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MLXBF_GIGE_MDIO_CORE_R_SHIFT;
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core_od = (reg2 & MLXBF_GIGE_MDIO_CORE_OD_MASK) >>
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MLXBF_GIGE_MDIO_CORE_OD_SHIFT;
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/* Compute PLL output frequency as follow:
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*
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* CORE_F / 16384
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* freq_output = freq_reference * ----------------------------
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* (CORE_R + 1) * (CORE_OD + 1)
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*/
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freq_output = div_u64((MLXBF_GIGE_MDIO_FREQ_REFERENCE * core_f),
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MLXBF_GIGE_MDIO_COREPLL_CONST);
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freq_output = div_u64(freq_output, (core_r + 1) * (core_od + 1));
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return freq_output;
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}
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/* Formula for encoding the MDIO period. The encoded value is
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* passed to the MDIO config register.
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*
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* mdc_clk = 2*(val + 1)*(core clock in sec)
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*
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* i1clk is in Hz:
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* 400 ns = 2*(val + 1)*(1/i1clk)
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*
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* val = (((400/10^9) / (1/i1clk) / 2) - 1)
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* val = (400/2 * i1clk)/10^9 - 1
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*/
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static u8 mdio_period_map(struct mlxbf_gige *priv)
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{
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u8 mdio_period;
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u64 i1clk;
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i1clk = calculate_i1clk(priv);
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mdio_period = div_u64((MLXBF_GIGE_MDC_CLK_NS >> 1) * i1clk, 1000000000) - 1;
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return mdio_period;
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}
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static u32 mlxbf_gige_mdio_create_cmd(struct mlxbf_gige_mdio_gw *mdio_gw, u16 data, int phy_add,
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int phy_reg, u32 opcode)
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{
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u32 gw_reg = 0;
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gw_reg |= ((data << mdio_gw->write_data.shift) &
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mdio_gw->write_data.mask);
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gw_reg |= ((phy_reg << mdio_gw->devad.shift) &
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mdio_gw->devad.mask);
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gw_reg |= ((phy_add << mdio_gw->partad.shift) &
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mdio_gw->partad.mask);
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gw_reg |= ((opcode << mdio_gw->opcode.shift) &
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mdio_gw->opcode.mask);
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gw_reg |= ((MLXBF_GIGE_MDIO_CL22_ST1 << mdio_gw->st1.shift) &
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mdio_gw->st1.mask);
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gw_reg |= ((MLXBF_GIGE_MDIO_SET_BUSY << mdio_gw->busy.shift) &
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mdio_gw->busy.mask);
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return gw_reg;
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}
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static int mlxbf_gige_mdio_read(struct mii_bus *bus, int phy_add, int phy_reg)
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{
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struct mlxbf_gige *priv = bus->priv;
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u32 cmd;
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int ret;
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u32 val;
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/* Send mdio read request */
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cmd = mlxbf_gige_mdio_create_cmd(priv->mdio_gw, 0, phy_add, phy_reg,
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MLXBF_GIGE_MDIO_CL22_READ);
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writel(cmd, priv->mdio_io + priv->mdio_gw->gw_address);
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ret = readl_poll_timeout_atomic(priv->mdio_io + priv->mdio_gw->gw_address,
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val, !(val & priv->mdio_gw->busy.mask),
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5, 1000000);
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if (ret) {
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writel(0, priv->mdio_io + priv->mdio_gw->gw_address);
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return ret;
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}
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ret = readl(priv->mdio_io + priv->mdio_gw->read_data_address);
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/* Only return ad bits of the gw register */
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ret &= priv->mdio_gw->read_data.mask;
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/* The MDIO lock is set on read. To release it, clear gw register */
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writel(0, priv->mdio_io + priv->mdio_gw->gw_address);
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return ret;
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}
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static int mlxbf_gige_mdio_write(struct mii_bus *bus, int phy_add,
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int phy_reg, u16 val)
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{
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struct mlxbf_gige *priv = bus->priv;
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u32 temp;
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u32 cmd;
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int ret;
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/* Send mdio write request */
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cmd = mlxbf_gige_mdio_create_cmd(priv->mdio_gw, val, phy_add, phy_reg,
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MLXBF_GIGE_MDIO_CL22_WRITE);
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writel(cmd, priv->mdio_io + priv->mdio_gw->gw_address);
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/* If the poll timed out, drop the request */
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ret = readl_poll_timeout_atomic(priv->mdio_io + priv->mdio_gw->gw_address,
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temp, !(temp & priv->mdio_gw->busy.mask),
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5, 1000000);
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/* The MDIO lock is set on read. To release it, clear gw register */
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writel(0, priv->mdio_io + priv->mdio_gw->gw_address);
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return ret;
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}
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static void mlxbf_gige_mdio_cfg(struct mlxbf_gige *priv)
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{
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u8 mdio_period;
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u32 val;
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mdio_period = mdio_period_map(priv);
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if (priv->hw_version == MLXBF_GIGE_VERSION_BF2) {
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val = MLXBF2_GIGE_MDIO_CFG_VAL;
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val |= FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDC_PERIOD_MASK, mdio_period);
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writel(val, priv->mdio_io + MLXBF2_GIGE_MDIO_CFG_OFFSET);
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} else {
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val = FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) |
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FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1);
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writel(val, priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG0);
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val = FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDC_PERIOD_MASK, mdio_period);
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writel(val, priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG1);
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val = FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) |
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FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13);
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writel(val, priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG2);
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}
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}
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int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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int ret;
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if (priv->hw_version > MLXBF_GIGE_VERSION_BF3)
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return -ENODEV;
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priv->mdio_io = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MDIO9);
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if (IS_ERR(priv->mdio_io))
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return PTR_ERR(priv->mdio_io);
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/* clk resource shared with other drivers so cannot use
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* devm_platform_ioremap_resource
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*/
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res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_CLK);
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if (!res) {
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/* For backward compatibility with older ACPI tables, also keep
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* CLK resource internal to the driver.
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*/
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res = &corepll_params[priv->hw_version];
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}
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priv->clk_io = devm_ioremap(dev, res->start, resource_size(res));
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if (!priv->clk_io)
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return -ENOMEM;
|
||
|
|
|
||
|
|
priv->mdio_gw = &mlxbf_gige_mdio_gw_t[priv->hw_version];
|
||
|
|
|
||
|
|
mlxbf_gige_mdio_cfg(priv);
|
||
|
|
|
||
|
|
priv->mdiobus = devm_mdiobus_alloc(dev);
|
||
|
|
if (!priv->mdiobus) {
|
||
|
|
dev_err(dev, "Failed to alloc MDIO bus\n");
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
priv->mdiobus->name = "mlxbf-mdio";
|
||
|
|
priv->mdiobus->read = mlxbf_gige_mdio_read;
|
||
|
|
priv->mdiobus->write = mlxbf_gige_mdio_write;
|
||
|
|
priv->mdiobus->parent = dev;
|
||
|
|
priv->mdiobus->priv = priv;
|
||
|
|
snprintf(priv->mdiobus->id, MII_BUS_ID_SIZE, "%s",
|
||
|
|
dev_name(dev));
|
||
|
|
|
||
|
|
ret = mdiobus_register(priv->mdiobus);
|
||
|
|
if (ret)
|
||
|
|
dev_err(dev, "Failed to register MDIO bus\n");
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
void mlxbf_gige_mdio_remove(struct mlxbf_gige *priv)
|
||
|
|
{
|
||
|
|
mdiobus_unregister(priv->mdiobus);
|
||
|
|
}
|