294 lines
7.3 KiB
C
294 lines
7.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* 10G controller driver for Samsung SoCs
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Siva Reddy Kallam <siva.kallam@samsung.com>
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*/
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#ifndef __SXGBE_DESC_H__
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#define __SXGBE_DESC_H__
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#define SXGBE_DESC_SIZE_BYTES 16
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/* forward declaration */
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struct sxgbe_extra_stats;
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/* Transmit checksum insertion control */
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enum tdes_csum_insertion {
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cic_disabled = 0, /* Checksum Insertion Control */
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cic_only_ip = 1, /* Only IP header */
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/* IP header but pseudoheader is not calculated */
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cic_no_pseudoheader = 2,
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cic_full = 3, /* IP header and pseudoheader */
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};
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struct sxgbe_tx_norm_desc {
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u64 tdes01; /* buf1 address */
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union {
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/* TX Read-Format Desc 2,3 */
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struct {
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/* TDES2 */
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u32 buf1_size:14;
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u32 vlan_tag_ctl:2;
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u32 buf2_size:14;
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u32 timestmp_enable:1;
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u32 int_on_com:1;
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/* TDES3 */
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union {
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u16 tcp_payload_len;
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struct {
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u32 total_pkt_len:15;
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u32 reserved1:1;
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} pkt_len;
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} tx_pkt_len;
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u16 cksum_ctl:2;
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u16 tse_bit:1;
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u16 tcp_hdr_len:4;
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u16 sa_insert_ctl:3;
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u16 crc_pad_ctl:2;
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u16 last_desc:1;
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u16 first_desc:1;
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u16 ctxt_bit:1;
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u16 own_bit:1;
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} tx_rd_des23;
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/* tx write back Desc 2,3 */
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struct {
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/* WB TES2 */
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u32 reserved1;
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/* WB TES3 */
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u32 reserved2:31;
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u32 own_bit:1;
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} tx_wb_des23;
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} tdes23;
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};
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struct sxgbe_rx_norm_desc {
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union {
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u64 rdes01; /* buf1 address */
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union {
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u32 out_vlan_tag:16;
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u32 in_vlan_tag:16;
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u32 rss_hash;
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} rx_wb_des01;
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} rdes01;
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union {
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/* RX Read format Desc 2,3 */
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struct{
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/* RDES2 */
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u64 buf2_addr:62;
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/* RDES3 */
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u32 int_on_com:1;
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u32 own_bit:1;
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} rx_rd_des23;
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/* RX write back */
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struct{
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/* WB RDES2 */
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u32 hdr_len:10;
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u32 rdes2_reserved:2;
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u32 elrd_val:1;
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u32 iovt_sel:1;
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u32 res_pkt:1;
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u32 vlan_filter_match:1;
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u32 sa_filter_fail:1;
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u32 da_filter_fail:1;
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u32 hash_filter_pass:1;
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u32 macaddr_filter_match:8;
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u32 l3_filter_match:1;
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u32 l4_filter_match:1;
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u32 l34_filter_num:3;
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/* WB RDES3 */
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u32 pkt_len:14;
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u32 rdes3_reserved:1;
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u32 err_summary:1;
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u32 err_l2_type:4;
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u32 layer34_pkt_type:4;
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u32 no_coagulation_pkt:1;
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u32 in_seq_pkt:1;
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u32 rss_valid:1;
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u32 context_des_avail:1;
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u32 last_desc:1;
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u32 first_desc:1;
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u32 recv_context_desc:1;
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u32 own_bit:1;
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} rx_wb_des23;
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} rdes23;
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};
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/* Context descriptor structure */
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struct sxgbe_tx_ctxt_desc {
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u32 tstamp_lo;
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u32 tstamp_hi;
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u32 maxseg_size:15;
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u32 reserved1:1;
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u32 ivlan_tag:16;
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u32 vlan_tag:16;
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u32 vltag_valid:1;
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u32 ivlan_tag_valid:1;
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u32 ivlan_tag_ctl:2;
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u32 reserved2:3;
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u32 ctxt_desc_err:1;
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u32 reserved3:2;
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u32 ostc:1;
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u32 tcmssv:1;
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u32 reserved4:2;
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u32 ctxt_bit:1;
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u32 own_bit:1;
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};
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struct sxgbe_rx_ctxt_desc {
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u32 tstamp_lo;
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u32 tstamp_hi;
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u32 reserved1;
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u32 ptp_msgtype:4;
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u32 tstamp_available:1;
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u32 ptp_rsp_err:1;
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u32 tstamp_dropped:1;
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u32 reserved2:23;
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u32 rx_ctxt_desc:1;
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u32 own_bit:1;
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};
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struct sxgbe_desc_ops {
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/* DMA TX descriptor ring initialization */
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void (*init_tx_desc)(struct sxgbe_tx_norm_desc *p);
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/* Invoked by the xmit function to prepare the tx descriptor */
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void (*tx_desc_enable_tse)(struct sxgbe_tx_norm_desc *p, u8 is_tse,
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u32 total_hdr_len, u32 tcp_hdr_len,
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u32 tcp_payload_len);
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/* Assign buffer lengths for descriptor */
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void (*prepare_tx_desc)(struct sxgbe_tx_norm_desc *p, u8 is_fd,
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int buf1_len, int pkt_len, int cksum);
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/* Set VLAN control information */
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void (*tx_vlanctl_desc)(struct sxgbe_tx_norm_desc *p, int vlan_ctl);
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/* Set the owner of the descriptor */
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void (*set_tx_owner)(struct sxgbe_tx_norm_desc *p);
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/* Get the owner of the descriptor */
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int (*get_tx_owner)(struct sxgbe_tx_norm_desc *p);
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/* Invoked by the xmit function to close the tx descriptor */
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void (*close_tx_desc)(struct sxgbe_tx_norm_desc *p);
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/* Clean the tx descriptor as soon as the tx irq is received */
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void (*release_tx_desc)(struct sxgbe_tx_norm_desc *p);
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/* Clear interrupt on tx frame completion. When this bit is
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* set an interrupt happens as soon as the frame is transmitted
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*/
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void (*clear_tx_ic)(struct sxgbe_tx_norm_desc *p);
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/* Last tx segment reports the transmit status */
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int (*get_tx_ls)(struct sxgbe_tx_norm_desc *p);
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/* Get the buffer size from the descriptor */
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int (*get_tx_len)(struct sxgbe_tx_norm_desc *p);
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/* Set tx timestamp enable bit */
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void (*tx_enable_tstamp)(struct sxgbe_tx_norm_desc *p);
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/* get tx timestamp status */
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int (*get_tx_timestamp_status)(struct sxgbe_tx_norm_desc *p);
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/* TX Context Descripto Specific */
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void (*tx_ctxt_desc_set_ctxt)(struct sxgbe_tx_ctxt_desc *p);
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/* Set the owner of the TX context descriptor */
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void (*tx_ctxt_desc_set_owner)(struct sxgbe_tx_ctxt_desc *p);
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/* Get the owner of the TX context descriptor */
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int (*get_tx_ctxt_owner)(struct sxgbe_tx_ctxt_desc *p);
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/* Set TX mss */
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void (*tx_ctxt_desc_set_mss)(struct sxgbe_tx_ctxt_desc *p, u16 mss);
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/* Set TX mss */
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int (*tx_ctxt_desc_get_mss)(struct sxgbe_tx_ctxt_desc *p);
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/* Set TX tcmssv */
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void (*tx_ctxt_desc_set_tcmssv)(struct sxgbe_tx_ctxt_desc *p);
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/* Reset TX ostc */
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void (*tx_ctxt_desc_reset_ostc)(struct sxgbe_tx_ctxt_desc *p);
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/* Set IVLAN information */
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void (*tx_ctxt_desc_set_ivlantag)(struct sxgbe_tx_ctxt_desc *p,
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int is_ivlanvalid, int ivlan_tag,
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int ivlan_ctl);
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/* Return IVLAN Tag */
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int (*tx_ctxt_desc_get_ivlantag)(struct sxgbe_tx_ctxt_desc *p);
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/* Set VLAN Tag */
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void (*tx_ctxt_desc_set_vlantag)(struct sxgbe_tx_ctxt_desc *p,
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int is_vlanvalid, int vlan_tag);
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/* Return VLAN Tag */
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int (*tx_ctxt_desc_get_vlantag)(struct sxgbe_tx_ctxt_desc *p);
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/* Set Time stamp */
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void (*tx_ctxt_set_tstamp)(struct sxgbe_tx_ctxt_desc *p,
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u8 ostc_enable, u64 tstamp);
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/* Close TX context descriptor */
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void (*close_tx_ctxt_desc)(struct sxgbe_tx_ctxt_desc *p);
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/* WB status of context descriptor */
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int (*get_tx_ctxt_cde)(struct sxgbe_tx_ctxt_desc *p);
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/* DMA RX descriptor ring initialization */
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void (*init_rx_desc)(struct sxgbe_rx_norm_desc *p, int disable_rx_ic,
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int mode, int end);
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/* Get own bit */
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int (*get_rx_owner)(struct sxgbe_rx_norm_desc *p);
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/* Set own bit */
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void (*set_rx_owner)(struct sxgbe_rx_norm_desc *p);
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/* Set Interrupt on completion bit */
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void (*set_rx_int_on_com)(struct sxgbe_rx_norm_desc *p);
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/* Get the receive frame size */
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int (*get_rx_frame_len)(struct sxgbe_rx_norm_desc *p);
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/* Return first Descriptor status */
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int (*get_rx_fd_status)(struct sxgbe_rx_norm_desc *p);
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/* Return first Descriptor status */
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int (*get_rx_ld_status)(struct sxgbe_rx_norm_desc *p);
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/* Return the reception status looking at the RDES1 */
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int (*rx_wbstatus)(struct sxgbe_rx_norm_desc *p,
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struct sxgbe_extra_stats *x, int *checksum);
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/* Get own bit */
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int (*get_rx_ctxt_owner)(struct sxgbe_rx_ctxt_desc *p);
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/* Set own bit */
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void (*set_rx_ctxt_owner)(struct sxgbe_rx_ctxt_desc *p);
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/* Return the reception status looking at Context control information */
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void (*rx_ctxt_wbstatus)(struct sxgbe_rx_ctxt_desc *p,
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struct sxgbe_extra_stats *x);
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/* Get rx timestamp status */
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int (*get_rx_ctxt_tstamp_status)(struct sxgbe_rx_ctxt_desc *p);
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/* Get timestamp value for rx, need to check this */
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u64 (*get_timestamp)(struct sxgbe_rx_ctxt_desc *p);
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};
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const struct sxgbe_desc_ops *sxgbe_get_desc_ops(void);
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#endif /* __SXGBE_DESC_H__ */
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