54 lines
1.7 KiB
C
54 lines
1.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2020, Intel Corporation
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* DWMAC Intel header file
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*/
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#ifndef __DWMAC_INTEL_H__
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#define __DWMAC_INTEL_H__
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#define POLL_DELAY_US 8
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/* SERDES Register */
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#define SERDES_GCR 0x0 /* Global Conguration */
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#define SERDES_GSR0 0x5 /* Global Status Reg0 */
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#define SERDES_GCR0 0xb /* Global Configuration Reg0 */
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/* SERDES defines */
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#define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
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#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
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#define SERDES_RST BIT(2) /* Serdes Reset */
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#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
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#define SERDES_RATE_MASK GENMASK(9, 8)
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#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */
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#define SERDES_LINK_MODE_MASK GENMASK(2, 1)
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#define SERDES_LINK_MODE_SHIFT 1
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#define SERDES_PWR_ST_SHIFT 4
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#define SERDES_PWR_ST_P0 0x0
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#define SERDES_PWR_ST_P3 0x3
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#define SERDES_LINK_MODE_2G5 0x3
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#define SERSED_LINK_MODE_1G 0x2
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#define SERDES_PCLK_37p5MHZ 0x0
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#define SERDES_PCLK_70MHZ 0x1
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#define SERDES_RATE_PCIE_GEN1 0x0
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#define SERDES_RATE_PCIE_GEN2 0x1
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#define SERDES_RATE_PCIE_SHIFT 8
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#define SERDES_PCLK_SHIFT 12
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#define INTEL_MGBE_ADHOC_ADDR 0x15
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#define INTEL_MGBE_XPCS_ADDR 0x16
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/* Cross-timestamping defines */
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#define ART_CPUID_LEAF 0x15
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#define EHL_PSE_ART_MHZ 19200000
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/* Selection for PTP Clock Freq belongs to PSE & PCH GbE */
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#define PSE_PTP_CLK_FREQ_MASK (GMAC_GPO0 | GMAC_GPO3)
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#define PSE_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0)
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#define PSE_PTP_CLK_FREQ_200MHZ (GMAC_GPO0 | GMAC_GPO3)
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#define PSE_PTP_CLK_FREQ_256MHZ (0)
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#define PCH_PTP_CLK_FREQ_MASK (GMAC_GPO0)
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#define PCH_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0)
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#define PCH_PTP_CLK_FREQ_200MHZ (0)
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#endif /* __DWMAC_INTEL_H__ */
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