142 lines
4.4 KiB
C
142 lines
4.4 KiB
C
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/* SPDX-License-Identifier: BSD-3-Clause-Clear */
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/*
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* Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef ATH12K_PCI_H
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#define ATH12K_PCI_H
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#include <linux/mhi.h>
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#include "core.h"
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#define PCIE_SOC_GLOBAL_RESET 0x3008
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#define PCIE_SOC_GLOBAL_RESET_V 1
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#define WLAON_WARM_SW_ENTRY 0x1f80504
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#define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c
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#define PCIE_Q6_COOKIE_ADDR 0x01f80500
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#define PCIE_Q6_COOKIE_DATA 0xc0000000
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/* register to wake the UMAC from power collapse */
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#define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040
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/* register used for handshake mechanism to validate UMAC is awake */
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#define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004
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#define PCIE_PCIE_PARF_LTSSM 0x1e081b0
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#define PARM_LTSSM_VALUE 0x111
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#define GCC_GCC_PCIE_HOT_RST 0x1e38338
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#define GCC_GCC_PCIE_HOT_RST_VAL 0x10
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#define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228
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#define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2
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#define PCIE_INT_CLEAR_ALL 0xffffffff
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#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab) \
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((ab)->hw_params->regs->pcie_qserdes_sysclk_en_sel)
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#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10
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#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff
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#define PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab) \
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((ab)->hw_params->regs->pcie_pcs_osc_dtct_config_base)
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#define PCIE_PCS_OSC_DTCT_CONFIG1_VAL 0x02
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#define PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab) \
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((ab)->hw_params->regs->pcie_pcs_osc_dtct_config_base + 0x4)
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#define PCIE_PCS_OSC_DTCT_CONFIG2_VAL 0x52
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#define PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab) \
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((ab)->hw_params->regs->pcie_pcs_osc_dtct_config_base + 0xc)
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#define PCIE_PCS_OSC_DTCT_CONFIG4_VAL 0xff
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#define PCIE_PCS_OSC_DTCT_CONFIG_MSK 0x000000ff
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#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
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#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
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#define PCI_BAR_WINDOW0_BASE 0x1E00000
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#define PCI_BAR_WINDOW0_END 0x1E7FFFC
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#define PCI_SOC_RANGE_MASK 0x3FFF
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#define PCI_SOC_PCI_REG_BASE 0x1E04000
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#define PCI_SOC_PCI_REG_END 0x1E07FFC
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#define PCI_PARF_BASE 0x1E08000
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#define PCI_PARF_END 0x1E0BFFC
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#define PCI_MHIREGLEN_REG 0x1E0E100
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#define PCI_MHI_REGION_END 0x1E0EFFC
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#define QRTR_PCI_DOMAIN_NR_MASK GENMASK(7, 4)
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#define QRTR_PCI_BUS_NUMBER_MASK GENMASK(3, 0)
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#define ATH12K_PCI_SOC_HW_VERSION_1 1
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#define ATH12K_PCI_SOC_HW_VERSION_2 2
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struct ath12k_msi_user {
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const char *name;
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int num_vectors;
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u32 base_vector;
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};
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struct ath12k_msi_config {
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int total_vectors;
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int total_users;
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const struct ath12k_msi_user *users;
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};
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enum ath12k_pci_flags {
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ATH12K_PCI_FLAG_INIT_DONE,
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ATH12K_PCI_FLAG_IS_MSI_64,
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ATH12K_PCI_ASPM_RESTORE,
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};
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struct ath12k_pci_ops {
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int (*wakeup)(struct ath12k_base *ab);
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void (*release)(struct ath12k_base *ab);
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};
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struct ath12k_pci {
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struct pci_dev *pdev;
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struct ath12k_base *ab;
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u16 dev_id;
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char amss_path[100];
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u32 msi_ep_base_data;
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struct mhi_controller *mhi_ctrl;
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const struct ath12k_msi_config *msi_config;
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unsigned long mhi_state;
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u32 register_window;
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/* protects register_window above */
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spinlock_t window_lock;
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/* enum ath12k_pci_flags */
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unsigned long flags;
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u16 link_ctl;
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const struct ath12k_pci_ops *pci_ops;
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};
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static inline struct ath12k_pci *ath12k_pci_priv(struct ath12k_base *ab)
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{
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return (struct ath12k_pci *)ab->drv_priv;
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}
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int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name,
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int *num_vectors, u32 *user_base_data,
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u32 *base_vector);
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int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector);
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void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value);
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u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset);
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int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id,
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u8 *ul_pipe, u8 *dl_pipe);
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void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo,
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u32 *msi_addr_hi);
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void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id,
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u32 *msi_idx);
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void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab);
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void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab);
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void ath12k_pci_ext_irq_enable(struct ath12k_base *ab);
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void ath12k_pci_ext_irq_disable(struct ath12k_base *ab);
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int ath12k_pci_hif_suspend(struct ath12k_base *ab);
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int ath12k_pci_hif_resume(struct ath12k_base *ab);
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void ath12k_pci_stop(struct ath12k_base *ab);
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int ath12k_pci_start(struct ath12k_base *ab);
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int ath12k_pci_power_up(struct ath12k_base *ab);
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void ath12k_pci_power_down(struct ath12k_base *ab);
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#endif /* ATH12K_PCI_H */
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