185 lines
5.8 KiB
C
185 lines
5.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* Copyright (C) 2017 Intel Deutschland GmbH
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* Copyright (C) 2018-2020 Intel Corporation
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*/
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#ifndef __iwl_context_info_file_h__
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#define __iwl_context_info_file_h__
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/* maximmum number of DRAM map entries supported by FW */
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#define IWL_MAX_DRAM_ENTRY 64
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#define CSR_CTXT_INFO_BA 0x40
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/**
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* enum iwl_context_info_flags - Context information control flags
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* @IWL_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting
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* the init done for driver command that configures several system modes
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* @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug
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* @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump
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* @IWL_CTXT_INFO_RB_CB_SIZE: mask of the RBD Cyclic Buffer Size
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* exponent, the actual size is 2**value, valid sizes are 8-2048.
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* The value is four bits long. Maximum valid exponent is 12
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* @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the
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* default is short format - not supported by the driver)
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* @IWL_CTXT_INFO_RB_SIZE: RB size mask
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* (values are IWL_CTXT_INFO_RB_SIZE_*K)
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* @IWL_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size
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* @IWL_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size
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* @IWL_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size
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* @IWL_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size
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* @IWL_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size
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* @IWL_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size
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* @IWL_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size
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* @IWL_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size
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* @IWL_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size
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* @IWL_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size
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*/
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enum iwl_context_info_flags {
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IWL_CTXT_INFO_AUTO_FUNC_INIT = 0x0001,
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IWL_CTXT_INFO_EARLY_DEBUG = 0x0002,
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IWL_CTXT_INFO_ENABLE_CDMP = 0x0004,
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IWL_CTXT_INFO_RB_CB_SIZE = 0x00f0,
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IWL_CTXT_INFO_TFD_FORMAT_LONG = 0x0100,
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IWL_CTXT_INFO_RB_SIZE = 0x1e00,
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IWL_CTXT_INFO_RB_SIZE_1K = 0x1,
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IWL_CTXT_INFO_RB_SIZE_2K = 0x2,
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IWL_CTXT_INFO_RB_SIZE_4K = 0x4,
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IWL_CTXT_INFO_RB_SIZE_8K = 0x8,
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IWL_CTXT_INFO_RB_SIZE_12K = 0x9,
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IWL_CTXT_INFO_RB_SIZE_16K = 0xa,
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IWL_CTXT_INFO_RB_SIZE_20K = 0xb,
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IWL_CTXT_INFO_RB_SIZE_24K = 0xc,
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IWL_CTXT_INFO_RB_SIZE_28K = 0xd,
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IWL_CTXT_INFO_RB_SIZE_32K = 0xe,
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};
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/*
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* struct iwl_context_info_version - version structure
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* @mac_id: SKU and revision id
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* @version: context information version id
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* @size: the size of the context information in DWs
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*/
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struct iwl_context_info_version {
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__le16 mac_id;
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__le16 version;
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__le16 size;
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__le16 reserved;
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} __packed;
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/*
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* struct iwl_context_info_control - version structure
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* @control_flags: context information flags see &enum iwl_context_info_flags
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*/
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struct iwl_context_info_control {
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__le32 control_flags;
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__le32 reserved;
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} __packed;
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/*
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* struct iwl_context_info_dram - images DRAM map
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* each entry in the map represents a DRAM chunk of up to 32 KB
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* @umac_img: UMAC image DRAM map
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* @lmac_img: LMAC image DRAM map
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* @virtual_img: paged image DRAM map
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*/
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struct iwl_context_info_dram {
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__le64 umac_img[IWL_MAX_DRAM_ENTRY];
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__le64 lmac_img[IWL_MAX_DRAM_ENTRY];
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__le64 virtual_img[IWL_MAX_DRAM_ENTRY];
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} __packed;
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/*
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* struct iwl_context_info_rbd_cfg - RBDs configuration
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* @free_rbd_addr: default queue free RB CB base address
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* @used_rbd_addr: default queue used RB CB base address
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* @status_wr_ptr: default queue used RB status write pointer
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*/
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struct iwl_context_info_rbd_cfg {
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__le64 free_rbd_addr;
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__le64 used_rbd_addr;
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__le64 status_wr_ptr;
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} __packed;
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/*
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* struct iwl_context_info_hcmd_cfg - command queue configuration
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* @cmd_queue_addr: address of command queue
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* @cmd_queue_size: number of entries
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*/
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struct iwl_context_info_hcmd_cfg {
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__le64 cmd_queue_addr;
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u8 cmd_queue_size;
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u8 reserved[7];
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} __packed;
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/*
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* struct iwl_context_info_dump_cfg - Core Dump configuration
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* @core_dump_addr: core dump (debug DRAM address) start address
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* @core_dump_size: size, in DWs
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*/
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struct iwl_context_info_dump_cfg {
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__le64 core_dump_addr;
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__le32 core_dump_size;
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__le32 reserved;
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} __packed;
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/*
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* struct iwl_context_info_pnvm_cfg - platform NVM data configuration
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* @platform_nvm_addr: Platform NVM data start address
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* @platform_nvm_size: size in DWs
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*/
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struct iwl_context_info_pnvm_cfg {
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__le64 platform_nvm_addr;
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__le32 platform_nvm_size;
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__le32 reserved;
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} __packed;
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/*
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* struct iwl_context_info_early_dbg_cfg - early debug configuration for
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* dumping DRAM addresses
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* @early_debug_addr: early debug start address
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* @early_debug_size: size in DWs
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*/
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struct iwl_context_info_early_dbg_cfg {
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__le64 early_debug_addr;
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__le32 early_debug_size;
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__le32 reserved;
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} __packed;
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/*
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* struct iwl_context_info - device INIT configuration
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* @version: version information of context info and HW
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* @control: control flags of FH configurations
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* @rbd_cfg: default RX queue configuration
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* @hcmd_cfg: command queue configuration
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* @dump_cfg: core dump data
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* @edbg_cfg: early debug configuration
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* @pnvm_cfg: platform nvm configuration
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* @dram: firmware image addresses in DRAM
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*/
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struct iwl_context_info {
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struct iwl_context_info_version version;
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struct iwl_context_info_control control;
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__le64 reserved0;
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struct iwl_context_info_rbd_cfg rbd_cfg;
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struct iwl_context_info_hcmd_cfg hcmd_cfg;
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__le32 reserved1[4];
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struct iwl_context_info_dump_cfg dump_cfg;
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struct iwl_context_info_early_dbg_cfg edbg_cfg;
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struct iwl_context_info_pnvm_cfg pnvm_cfg;
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__le32 reserved2[16];
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struct iwl_context_info_dram dram;
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__le32 reserved3[16];
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} __packed;
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int iwl_pcie_ctxt_info_init(struct iwl_trans *trans, const struct fw_img *fw);
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void iwl_pcie_ctxt_info_free(struct iwl_trans *trans);
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void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans);
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int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
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const struct fw_img *fw,
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struct iwl_context_info_dram *ctxt_dram);
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int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
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const void *data, u32 len,
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struct iwl_dram_data *dram);
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#endif /* __iwl_context_info_file_h__ */
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