46 lines
1.5 KiB
C
46 lines
1.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (c) 2018 Quantenna Communications */
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#ifndef __TOPAZ_PCIE_H
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#define __TOPAZ_PCIE_H
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/* Topaz PCIe DMA registers */
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#define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc)
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#define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4)
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#define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8)
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#define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc)
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#define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0)
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#define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4)
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#define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310)
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#define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319)
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#define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c)
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#define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324)
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#define PCIE_DMA_RD_ERR_STATUS_HIGH(base) ((base) + 0x328)
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#define PCIE_DMA_RD_DONE_IMWR_ADDR_LOW(base) ((base) + 0x33c)
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#define PCIE_DMA_RD_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x340)
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/* Topaz LHost IPC4 interrupt */
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#define TOPAZ_LH_IPC4_INT(base) ((base) + 0x13C)
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#define TOPAZ_LH_IPC4_INT_MASK(base) ((base) + 0x140)
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#define TOPAZ_RC_TX_DONE_IRQ (0)
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#define TOPAZ_RC_RST_EP_IRQ (1)
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#define TOPAZ_RC_TX_STOP_IRQ (2)
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#define TOPAZ_RC_RX_DONE_IRQ (3)
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#define TOPAZ_RC_PM_EP_IRQ (4)
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/* Topaz LHost M2L interrupt */
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#define TOPAZ_CTL_M2L_INT(base) ((base) + 0x2C)
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#define TOPAZ_CTL_M2L_INT_MASK(base) ((base) + 0x30)
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#define TOPAZ_RC_CTRL_IRQ (6)
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#define TOPAZ_IPC_IRQ_WORD(irq) (BIT(irq) | BIT(irq + 16))
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/* PCIe legacy INTx */
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#define TOPAZ_PCIE_CFG0_OFFSET (0x6C)
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#define TOPAZ_ASSERT_INTX BIT(9)
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#endif /* __TOPAZ_PCIE_H */
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