181 lines
5.8 KiB
C
181 lines
5.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright (c) 2021, MediaTek Inc.
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* Copyright (c) 2021-2022, Intel Corporation.
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*
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* Authors:
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* Haijun Liu <haijun.liu@mediatek.com>
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* Moises Veleta <moises.veleta@intel.com>
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* Ricardo Martinez <ricardo.martinez@linux.intel.com>
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*
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* Contributors:
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* Amir Hanania <amir.hanania@intel.com>
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* Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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* Sreehari Kancharla <sreehari.kancharla@intel.com>
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*/
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#ifndef __T7XX_CLDMA_H__
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#define __T7XX_CLDMA_H__
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#include <linux/bits.h>
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#include <linux/types.h>
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#define CLDMA_TXQ_NUM 8
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#define CLDMA_RXQ_NUM 8
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#define CLDMA_ALL_Q GENMASK(7, 0)
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/* Interrupt status bits */
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#define EMPTY_STATUS_BITMASK GENMASK(15, 8)
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#define TXRX_STATUS_BITMASK GENMASK(7, 0)
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#define EQ_STA_BIT_OFFSET 8
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#define L2_INT_BIT_COUNT 16
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#define EQ_STA_BIT(index) (BIT((index) + EQ_STA_BIT_OFFSET) & EMPTY_STATUS_BITMASK)
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#define TQ_ERR_INT_BITMASK GENMASK(23, 16)
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#define TQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24)
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#define RQ_ERR_INT_BITMASK GENMASK(23, 16)
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#define RQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24)
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#define CLDMA0_AO_BASE 0x10049000
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#define CLDMA0_PD_BASE 0x1021d000
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#define CLDMA1_AO_BASE 0x1004b000
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#define CLDMA1_PD_BASE 0x1021f000
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#define CLDMA_R_AO_BASE 0x10023000
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#define CLDMA_R_PD_BASE 0x1023d000
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/* CLDMA TX */
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#define REG_CLDMA_UL_START_ADDRL_0 0x0004
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#define REG_CLDMA_UL_START_ADDRH_0 0x0008
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#define REG_CLDMA_UL_CURRENT_ADDRL_0 0x0044
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#define REG_CLDMA_UL_CURRENT_ADDRH_0 0x0048
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#define REG_CLDMA_UL_STATUS 0x0084
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#define REG_CLDMA_UL_START_CMD 0x0088
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#define REG_CLDMA_UL_RESUME_CMD 0x008c
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#define REG_CLDMA_UL_STOP_CMD 0x0090
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#define REG_CLDMA_UL_ERROR 0x0094
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#define REG_CLDMA_UL_CFG 0x0098
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#define UL_CFG_BIT_MODE_36 BIT(5)
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#define UL_CFG_BIT_MODE_40 BIT(6)
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#define UL_CFG_BIT_MODE_64 BIT(7)
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#define UL_CFG_BIT_MODE_MASK GENMASK(7, 5)
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#define REG_CLDMA_UL_MEM 0x009c
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#define UL_MEM_CHECK_DIS BIT(0)
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/* CLDMA RX */
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#define REG_CLDMA_DL_START_CMD 0x05bc
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#define REG_CLDMA_DL_RESUME_CMD 0x05c0
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#define REG_CLDMA_DL_STOP_CMD 0x05c4
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#define REG_CLDMA_DL_MEM 0x0508
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#define DL_MEM_CHECK_DIS BIT(0)
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#define REG_CLDMA_DL_CFG 0x0404
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#define DL_CFG_UP_HW_LAST BIT(2)
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#define DL_CFG_BIT_MODE_36 BIT(10)
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#define DL_CFG_BIT_MODE_40 BIT(11)
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#define DL_CFG_BIT_MODE_64 BIT(12)
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#define DL_CFG_BIT_MODE_MASK GENMASK(12, 10)
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#define REG_CLDMA_DL_START_ADDRL_0 0x0478
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#define REG_CLDMA_DL_START_ADDRH_0 0x047c
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#define REG_CLDMA_DL_CURRENT_ADDRL_0 0x04b8
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#define REG_CLDMA_DL_CURRENT_ADDRH_0 0x04bc
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#define REG_CLDMA_DL_STATUS 0x04f8
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/* CLDMA MISC */
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#define REG_CLDMA_L2TISAR0 0x0810
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#define REG_CLDMA_L2TISAR1 0x0814
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#define REG_CLDMA_L2TIMR0 0x0818
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#define REG_CLDMA_L2TIMR1 0x081c
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#define REG_CLDMA_L2TIMCR0 0x0820
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#define REG_CLDMA_L2TIMCR1 0x0824
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#define REG_CLDMA_L2TIMSR0 0x0828
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#define REG_CLDMA_L2TIMSR1 0x082c
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#define REG_CLDMA_L3TISAR0 0x0830
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#define REG_CLDMA_L3TISAR1 0x0834
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#define REG_CLDMA_L2RISAR0 0x0850
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#define REG_CLDMA_L2RISAR1 0x0854
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#define REG_CLDMA_L3RISAR0 0x0870
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#define REG_CLDMA_L3RISAR1 0x0874
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#define REG_CLDMA_IP_BUSY 0x08b4
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#define IP_BUSY_WAKEUP BIT(0)
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#define CLDMA_L2TISAR0_ALL_INT_MASK GENMASK(15, 0)
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#define CLDMA_L2RISAR0_ALL_INT_MASK GENMASK(15, 0)
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/* CLDMA MISC */
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#define REG_CLDMA_L2RIMR0 0x0858
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#define REG_CLDMA_L2RIMR1 0x085c
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#define REG_CLDMA_L2RIMCR0 0x0860
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#define REG_CLDMA_L2RIMCR1 0x0864
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#define REG_CLDMA_L2RIMSR0 0x0868
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#define REG_CLDMA_L2RIMSR1 0x086c
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#define REG_CLDMA_BUSY_MASK 0x0954
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#define BUSY_MASK_PCIE BIT(0)
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#define BUSY_MASK_AP BIT(1)
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#define BUSY_MASK_MD BIT(2)
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#define REG_CLDMA_INT_MASK 0x0960
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/* CLDMA RESET */
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#define REG_INFRA_RST4_SET 0x0730
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#define RST4_CLDMA1_SW_RST_SET BIT(20)
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#define REG_INFRA_RST4_CLR 0x0734
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#define RST4_CLDMA1_SW_RST_CLR BIT(20)
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#define REG_INFRA_RST2_SET 0x0140
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#define RST2_PMIC_SW_RST_SET BIT(18)
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#define REG_INFRA_RST2_CLR 0x0144
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#define RST2_PMIC_SW_RST_CLR BIT(18)
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enum mtk_txrx {
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MTK_TX,
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MTK_RX,
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};
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enum t7xx_hw_mode {
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MODE_BIT_32,
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MODE_BIT_36,
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MODE_BIT_40,
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MODE_BIT_64,
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};
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struct t7xx_cldma_hw {
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enum t7xx_hw_mode hw_mode;
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void __iomem *ap_ao_base;
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void __iomem *ap_pdn_base;
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u32 phy_interrupt_id;
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};
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void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx);
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void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx);
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void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx);
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void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx);
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unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx);
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void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info);
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void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx);
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void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info);
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void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
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enum mtk_txrx tx_rx);
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void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask);
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void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask);
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void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx);
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void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info,
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unsigned int qno, u64 address, enum mtk_txrx tx_rx);
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void t7xx_cldma_hw_reset(void __iomem *ao_base);
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void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx);
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unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask,
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enum mtk_txrx tx_rx);
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void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info);
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void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info);
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bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno);
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#endif
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