180 lines
6.2 KiB
C
180 lines
6.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright (c) 2021, MediaTek Inc.
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* Copyright (c) 2021-2022, Intel Corporation.
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*
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* Authors:
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* Amir Hanania <amir.hanania@intel.com>
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* Haijun Liu <haijun.liu@mediatek.com>
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* Moises Veleta <moises.veleta@intel.com>
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* Ricardo Martinez <ricardo.martinez@linux.intel.com>
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*
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* Contributors:
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* Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
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* Eliot Lee <eliot.lee@intel.com>
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* Sreehari Kancharla <sreehari.kancharla@intel.com>
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*/
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#ifndef __T7XX_DPMAIF_H__
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#define __T7XX_DPMAIF_H__
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#include <linux/bits.h>
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#include <linux/types.h>
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#define DPMAIF_DL_PIT_SEQ_VALUE 251
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#define DPMAIF_UL_DRB_SIZE_WORD 4
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#define DPMAIF_MAX_CHECK_COUNT 1000000
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#define DPMAIF_CHECK_TIMEOUT_US 10000
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#define DPMAIF_CHECK_INIT_TIMEOUT_US 100000
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#define DPMAIF_CHECK_DELAY_US 10
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#define DPMAIF_RXQ_NUM 2
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#define DPMAIF_TXQ_NUM 5
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struct dpmaif_isr_en_mask {
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unsigned int ap_ul_l2intr_en_msk;
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unsigned int ap_dl_l2intr_en_msk;
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unsigned int ap_udl_ip_busy_en_msk;
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unsigned int ap_dl_l2intr_err_en_msk;
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};
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struct dpmaif_ul {
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bool que_started;
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unsigned char reserved[3];
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dma_addr_t drb_base;
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unsigned int drb_size_cnt;
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};
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struct dpmaif_dl {
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bool que_started;
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unsigned char reserved[3];
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dma_addr_t pit_base;
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unsigned int pit_size_cnt;
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dma_addr_t bat_base;
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unsigned int bat_size_cnt;
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dma_addr_t frg_base;
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unsigned int frg_size_cnt;
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unsigned int pit_seq;
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};
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struct dpmaif_hw_info {
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struct device *dev;
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void __iomem *pcie_base;
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struct dpmaif_dl dl_que[DPMAIF_RXQ_NUM];
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struct dpmaif_ul ul_que[DPMAIF_TXQ_NUM];
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struct dpmaif_isr_en_mask isr_en_mask;
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};
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/* DPMAIF HW Initialization parameter structure */
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struct dpmaif_hw_params {
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/* UL part */
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dma_addr_t drb_base_addr[DPMAIF_TXQ_NUM];
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unsigned int drb_size_cnt[DPMAIF_TXQ_NUM];
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/* DL part */
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dma_addr_t pkt_bat_base_addr[DPMAIF_RXQ_NUM];
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unsigned int pkt_bat_size_cnt[DPMAIF_RXQ_NUM];
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dma_addr_t frg_bat_base_addr[DPMAIF_RXQ_NUM];
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unsigned int frg_bat_size_cnt[DPMAIF_RXQ_NUM];
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dma_addr_t pit_base_addr[DPMAIF_RXQ_NUM];
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unsigned int pit_size_cnt[DPMAIF_RXQ_NUM];
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};
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enum dpmaif_hw_intr_type {
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DPF_INTR_INVALID_MIN,
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DPF_INTR_UL_DONE,
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DPF_INTR_UL_DRB_EMPTY,
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DPF_INTR_UL_MD_NOTREADY,
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DPF_INTR_UL_MD_PWR_NOTREADY,
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DPF_INTR_UL_LEN_ERR,
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DPF_INTR_DL_DONE,
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DPF_INTR_DL_SKB_LEN_ERR,
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DPF_INTR_DL_BATCNT_LEN_ERR,
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DPF_INTR_DL_PITCNT_LEN_ERR,
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DPF_INTR_DL_PKT_EMPTY_SET,
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DPF_INTR_DL_FRG_EMPTY_SET,
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DPF_INTR_DL_MTU_ERR,
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DPF_INTR_DL_FRGCNT_LEN_ERR,
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DPF_INTR_DL_Q0_PITCNT_LEN_ERR,
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DPF_INTR_DL_Q1_PITCNT_LEN_ERR,
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DPF_INTR_DL_HPC_ENT_TYPE_ERR,
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DPF_INTR_DL_Q0_DONE,
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DPF_INTR_DL_Q1_DONE,
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DPF_INTR_INVALID_MAX
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};
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#define DPF_RX_QNO0 0
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#define DPF_RX_QNO1 1
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#define DPF_RX_QNO_DFT DPF_RX_QNO0
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struct dpmaif_hw_intr_st_para {
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unsigned int intr_cnt;
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enum dpmaif_hw_intr_type intr_types[DPF_INTR_INVALID_MAX - 1];
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unsigned int intr_queues[DPF_INTR_INVALID_MAX - 1];
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};
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#define DPMAIF_HW_BAT_REMAIN 64
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#define DPMAIF_HW_BAT_PKTBUF (128 * 28)
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#define DPMAIF_HW_FRG_PKTBUF 128
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#define DPMAIF_HW_BAT_RSVLEN 64
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#define DPMAIF_HW_PKT_BIDCNT 1
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#define DPMAIF_HW_MTU_SIZE (3 * 1024 + 8)
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#define DPMAIF_HW_CHK_BAT_NUM 62
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#define DPMAIF_HW_CHK_FRG_NUM 3
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#define DPMAIF_HW_CHK_PIT_NUM (2 * DPMAIF_HW_CHK_BAT_NUM)
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#define DP_UL_INT_DONE_OFFSET 0
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#define DP_UL_INT_QDONE_MSK GENMASK(4, 0)
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#define DP_UL_INT_EMPTY_MSK GENMASK(9, 5)
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#define DP_UL_INT_MD_NOTREADY_MSK GENMASK(14, 10)
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#define DP_UL_INT_MD_PWR_NOTREADY_MSK GENMASK(19, 15)
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#define DP_UL_INT_ERR_MSK GENMASK(24, 20)
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#define DP_DL_INT_QDONE_MSK BIT(0)
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#define DP_DL_INT_SKB_LEN_ERR BIT(1)
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#define DP_DL_INT_BATCNT_LEN_ERR BIT(2)
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#define DP_DL_INT_PITCNT_LEN_ERR BIT(3)
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#define DP_DL_INT_PKT_EMPTY_MSK BIT(4)
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#define DP_DL_INT_FRG_EMPTY_MSK BIT(5)
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#define DP_DL_INT_MTU_ERR_MSK BIT(6)
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#define DP_DL_INT_FRG_LEN_ERR_MSK BIT(7)
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#define DP_DL_INT_Q0_PITCNT_LEN_ERR BIT(8)
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#define DP_DL_INT_Q1_PITCNT_LEN_ERR BIT(9)
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#define DP_DL_INT_HPC_ENT_TYPE_ERR BIT(10)
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#define DP_DL_INT_Q0_DONE BIT(13)
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#define DP_DL_INT_Q1_DONE BIT(14)
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#define DP_DL_Q0_STATUS_MASK (DP_DL_INT_Q0_PITCNT_LEN_ERR | DP_DL_INT_Q0_DONE)
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#define DP_DL_Q1_STATUS_MASK (DP_DL_INT_Q1_PITCNT_LEN_ERR | DP_DL_INT_Q1_DONE)
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int t7xx_dpmaif_hw_init(struct dpmaif_hw_info *hw_info, struct dpmaif_hw_params *init_param);
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int t7xx_dpmaif_hw_stop_all_txq(struct dpmaif_hw_info *hw_info);
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int t7xx_dpmaif_hw_stop_all_rxq(struct dpmaif_hw_info *hw_info);
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void t7xx_dpmaif_start_hw(struct dpmaif_hw_info *hw_info);
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int t7xx_dpmaif_hw_get_intr_cnt(struct dpmaif_hw_info *hw_info,
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struct dpmaif_hw_intr_st_para *para, int qno);
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void t7xx_dpmaif_unmask_ulq_intr(struct dpmaif_hw_info *hw_info, unsigned int q_num);
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void t7xx_dpmaif_ul_update_hw_drb_cnt(struct dpmaif_hw_info *hw_info, unsigned int q_num,
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unsigned int drb_entry_cnt);
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int t7xx_dpmaif_dl_snd_hw_bat_cnt(struct dpmaif_hw_info *hw_info, unsigned int bat_entry_cnt);
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int t7xx_dpmaif_dl_snd_hw_frg_cnt(struct dpmaif_hw_info *hw_info, unsigned int frg_entry_cnt);
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int t7xx_dpmaif_dlq_add_pit_remain_cnt(struct dpmaif_hw_info *hw_info, unsigned int dlq_pit_idx,
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unsigned int pit_remain_cnt);
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void t7xx_dpmaif_dlq_unmask_pitcnt_len_err_intr(struct dpmaif_hw_info *hw_info,
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unsigned int qno);
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void t7xx_dpmaif_dlq_unmask_rx_done(struct dpmaif_hw_info *hw_info, unsigned int qno);
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bool t7xx_dpmaif_ul_clr_done(struct dpmaif_hw_info *hw_info, unsigned int qno);
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void t7xx_dpmaif_ul_clr_all_intr(struct dpmaif_hw_info *hw_info);
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void t7xx_dpmaif_dl_clr_all_intr(struct dpmaif_hw_info *hw_info);
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void t7xx_dpmaif_clr_ip_busy_sts(struct dpmaif_hw_info *hw_info);
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void t7xx_dpmaif_dl_unmask_batcnt_len_err_intr(struct dpmaif_hw_info *hw_info);
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void t7xx_dpmaif_dl_unmask_pitcnt_len_err_intr(struct dpmaif_hw_info *hw_info);
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unsigned int t7xx_dpmaif_ul_get_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num);
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unsigned int t7xx_dpmaif_dl_get_bat_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num);
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unsigned int t7xx_dpmaif_dl_get_bat_wr_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num);
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unsigned int t7xx_dpmaif_dl_get_frg_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num);
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unsigned int t7xx_dpmaif_dl_dlq_pit_get_wr_idx(struct dpmaif_hw_info *hw_info,
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unsigned int dlq_pit_idx);
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#endif /* __T7XX_DPMAIF_H__ */
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