127 lines
3.6 KiB
C
127 lines
3.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Purpose: PCI Express Port Bus Driver's Internal Data Structures
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*
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* Copyright (C) 2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#ifndef _PORTDRV_H_
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#define _PORTDRV_H_
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#include <linux/compiler.h>
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/* Service Type */
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#define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */
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#define PCIE_PORT_SERVICE_PME (1 << PCIE_PORT_SERVICE_PME_SHIFT)
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#define PCIE_PORT_SERVICE_AER_SHIFT 1 /* Advanced Error Reporting */
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#define PCIE_PORT_SERVICE_AER (1 << PCIE_PORT_SERVICE_AER_SHIFT)
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#define PCIE_PORT_SERVICE_HP_SHIFT 2 /* Native Hotplug */
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#define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT)
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#define PCIE_PORT_SERVICE_DPC_SHIFT 3 /* Downstream Port Containment */
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#define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT)
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#define PCIE_PORT_SERVICE_BWNOTIF_SHIFT 4 /* Bandwidth notification */
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#define PCIE_PORT_SERVICE_BWNOTIF (1 << PCIE_PORT_SERVICE_BWNOTIF_SHIFT)
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#define PCIE_PORT_DEVICE_MAXSERVICES 5
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extern bool pcie_ports_dpc_native;
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#ifdef CONFIG_PCIEAER
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int pcie_aer_init(void);
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int pcie_aer_is_native(struct pci_dev *dev);
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#else
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static inline int pcie_aer_init(void) { return 0; }
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static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
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#endif
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#ifdef CONFIG_HOTPLUG_PCI_PCIE
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int pcie_hp_init(void);
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#else
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static inline int pcie_hp_init(void) { return 0; }
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#endif
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#ifdef CONFIG_PCIE_PME
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int pcie_pme_init(void);
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#else
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static inline int pcie_pme_init(void) { return 0; }
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#endif
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#ifdef CONFIG_PCIE_DPC
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int pcie_dpc_init(void);
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#else
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static inline int pcie_dpc_init(void) { return 0; }
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#endif
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/* Port Type */
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#define PCIE_ANY_PORT (~0)
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struct pcie_device {
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int irq; /* Service IRQ/MSI/MSI-X Vector */
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struct pci_dev *port; /* Root/Upstream/Downstream Port */
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u32 service; /* Port service this device represents */
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void *priv_data; /* Service Private Data */
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struct device device; /* Generic Device Interface */
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};
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#define to_pcie_device(d) container_of(d, struct pcie_device, device)
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static inline void set_service_data(struct pcie_device *dev, void *data)
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{
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dev->priv_data = data;
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}
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static inline void *get_service_data(struct pcie_device *dev)
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{
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return dev->priv_data;
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}
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struct pcie_port_service_driver {
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const char *name;
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int (*probe)(struct pcie_device *dev);
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void (*remove)(struct pcie_device *dev);
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int (*suspend)(struct pcie_device *dev);
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int (*resume_noirq)(struct pcie_device *dev);
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int (*resume)(struct pcie_device *dev);
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int (*runtime_suspend)(struct pcie_device *dev);
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int (*runtime_resume)(struct pcie_device *dev);
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int (*slot_reset)(struct pcie_device *dev);
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int port_type; /* Type of the port this driver can handle */
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u32 service; /* Port service this device represents */
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struct device_driver driver;
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};
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#define to_service_driver(d) \
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container_of(d, struct pcie_port_service_driver, driver)
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int pcie_port_service_register(struct pcie_port_service_driver *new);
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void pcie_port_service_unregister(struct pcie_port_service_driver *new);
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extern struct bus_type pcie_port_bus_type;
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struct pci_dev;
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#ifdef CONFIG_PCIE_PME
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extern bool pcie_pme_msi_disabled;
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static inline void pcie_pme_disable_msi(void)
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{
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pcie_pme_msi_disabled = true;
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}
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static inline bool pcie_pme_no_msi(void)
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{
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return pcie_pme_msi_disabled;
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}
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void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable);
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#else /* !CONFIG_PCIE_PME */
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static inline void pcie_pme_disable_msi(void) {}
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static inline bool pcie_pme_no_msi(void) { return false; }
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static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {}
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#endif /* !CONFIG_PCIE_PME */
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struct device *pcie_port_find_device(struct pci_dev *dev, u32 service);
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#endif /* _PORTDRV_H_ */
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