289 lines
8.3 KiB
C
289 lines
8.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 NXP
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#define IMX8MM_PCIE_PHY_CMN_REG061 0x184
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#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0)
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#define IMX8MM_PCIE_PHY_CMN_REG062 0x188
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#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3)
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#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C
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#define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6)
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#define IMX8MM_PCIE_PHY_CMN_REG064 0x190
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#define ANA_AUX_RX_TX_SEL_TX BIT(7)
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#define ANA_AUX_RX_TERM_GND_EN BIT(3)
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#define ANA_AUX_TX_TERM BIT(2)
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#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
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#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
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#define ANA_AUX_TX_LVL GENMASK(3, 0)
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#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
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#define ANA_PLL_DONE 0x3
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#define PCIE_PHY_TRSV_REG5 0x414
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#define PCIE_PHY_TRSV_REG6 0x418
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#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
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#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
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#define IMX8MM_GPR_PCIE_REF_CLK_EXT FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x2)
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#define IMX8MM_GPR_PCIE_AUX_EN BIT(19)
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#define IMX8MM_GPR_PCIE_CMN_RST BIT(18)
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#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17)
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#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
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#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
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enum imx8_pcie_phy_type {
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IMX8MM,
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IMX8MP,
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};
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struct imx8_pcie_phy_drvdata {
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const char *gpr;
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enum imx8_pcie_phy_type variant;
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};
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struct imx8_pcie_phy {
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void __iomem *base;
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struct clk *clk;
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struct phy *phy;
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struct regmap *iomuxc_gpr;
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struct reset_control *perst;
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struct reset_control *reset;
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u32 refclk_pad_mode;
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u32 tx_deemph_gen1;
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u32 tx_deemph_gen2;
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bool clkreq_unused;
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const struct imx8_pcie_phy_drvdata *drvdata;
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};
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static int imx8_pcie_phy_power_on(struct phy *phy)
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{
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int ret;
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u32 val, pad_mode;
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struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
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pad_mode = imx8_phy->refclk_pad_mode;
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switch (imx8_phy->drvdata->variant) {
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case IMX8MM:
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reset_control_assert(imx8_phy->reset);
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/* Tune PHY de-emphasis setting to pass PCIe compliance. */
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if (imx8_phy->tx_deemph_gen1)
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writel(imx8_phy->tx_deemph_gen1,
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imx8_phy->base + PCIE_PHY_TRSV_REG5);
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if (imx8_phy->tx_deemph_gen2)
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writel(imx8_phy->tx_deemph_gen2,
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imx8_phy->base + PCIE_PHY_TRSV_REG6);
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break;
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case IMX8MP: /* Do nothing. */
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break;
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}
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if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
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pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
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/* Configure the pad as input */
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val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
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writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
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imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
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} else {
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/* Configure the PHY to output the refclock via pad */
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writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
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imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
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}
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if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT ||
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pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
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/* Source clock from SoC internal PLL */
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writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,
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imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
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writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
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imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
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val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;
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writel(val | ANA_AUX_RX_TERM_GND_EN,
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imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);
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writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL,
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imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
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}
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/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
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regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
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IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
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imx8_phy->clkreq_unused ?
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0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
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regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
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IMX8MM_GPR_PCIE_AUX_EN,
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IMX8MM_GPR_PCIE_AUX_EN);
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regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
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IMX8MM_GPR_PCIE_POWER_OFF, 0);
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regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
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IMX8MM_GPR_PCIE_SSC_EN, 0);
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regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
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IMX8MM_GPR_PCIE_REF_CLK_SEL,
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pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
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IMX8MM_GPR_PCIE_REF_CLK_EXT :
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IMX8MM_GPR_PCIE_REF_CLK_PLL);
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usleep_range(100, 200);
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/* Do the PHY common block reset */
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regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
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IMX8MM_GPR_PCIE_CMN_RST,
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IMX8MM_GPR_PCIE_CMN_RST);
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switch (imx8_phy->drvdata->variant) {
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case IMX8MP:
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reset_control_deassert(imx8_phy->perst);
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fallthrough;
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case IMX8MM:
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reset_control_deassert(imx8_phy->reset);
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usleep_range(200, 500);
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break;
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}
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/* Polling to check the phy is ready or not. */
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ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
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val, val == ANA_PLL_DONE, 10, 20000);
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return ret;
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}
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static int imx8_pcie_phy_init(struct phy *phy)
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{
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struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
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return clk_prepare_enable(imx8_phy->clk);
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}
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static int imx8_pcie_phy_exit(struct phy *phy)
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{
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struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
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clk_disable_unprepare(imx8_phy->clk);
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return 0;
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}
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static const struct phy_ops imx8_pcie_phy_ops = {
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.init = imx8_pcie_phy_init,
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.exit = imx8_pcie_phy_exit,
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.power_on = imx8_pcie_phy_power_on,
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.owner = THIS_MODULE,
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};
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static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = {
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.gpr = "fsl,imx8mm-iomuxc-gpr",
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.variant = IMX8MM,
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};
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static const struct imx8_pcie_phy_drvdata imx8mp_drvdata = {
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.gpr = "fsl,imx8mp-iomuxc-gpr",
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.variant = IMX8MP,
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};
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static const struct of_device_id imx8_pcie_phy_of_match[] = {
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{.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata, },
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{.compatible = "fsl,imx8mp-pcie-phy", .data = &imx8mp_drvdata, },
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{ },
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};
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MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
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static int imx8_pcie_phy_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct imx8_pcie_phy *imx8_phy;
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struct resource *res;
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imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL);
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if (!imx8_phy)
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return -ENOMEM;
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imx8_phy->drvdata = of_device_get_match_data(dev);
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/* get PHY refclk pad mode */
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of_property_read_u32(np, "fsl,refclk-pad-mode",
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&imx8_phy->refclk_pad_mode);
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if (of_property_read_u32(np, "fsl,tx-deemph-gen1",
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&imx8_phy->tx_deemph_gen1))
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imx8_phy->tx_deemph_gen1 = 0;
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if (of_property_read_u32(np, "fsl,tx-deemph-gen2",
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&imx8_phy->tx_deemph_gen2))
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imx8_phy->tx_deemph_gen2 = 0;
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if (of_property_read_bool(np, "fsl,clkreq-unsupported"))
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imx8_phy->clkreq_unused = true;
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else
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imx8_phy->clkreq_unused = false;
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imx8_phy->clk = devm_clk_get(dev, "ref");
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if (IS_ERR(imx8_phy->clk)) {
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dev_err(dev, "failed to get imx pcie phy clock\n");
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return PTR_ERR(imx8_phy->clk);
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}
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/* Grab GPR config register range */
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imx8_phy->iomuxc_gpr =
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syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
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if (IS_ERR(imx8_phy->iomuxc_gpr)) {
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dev_err(dev, "unable to find iomuxc registers\n");
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return PTR_ERR(imx8_phy->iomuxc_gpr);
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}
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imx8_phy->reset = devm_reset_control_get_exclusive(dev, "pciephy");
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if (IS_ERR(imx8_phy->reset)) {
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dev_err(dev, "Failed to get PCIEPHY reset control\n");
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return PTR_ERR(imx8_phy->reset);
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}
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if (imx8_phy->drvdata->variant == IMX8MP) {
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imx8_phy->perst =
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devm_reset_control_get_exclusive(dev, "perst");
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if (IS_ERR(imx8_phy->perst))
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return dev_err_probe(dev, PTR_ERR(imx8_phy->perst),
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"Failed to get PCIE PHY PERST control\n");
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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imx8_phy->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(imx8_phy->base))
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return PTR_ERR(imx8_phy->base);
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imx8_phy->phy = devm_phy_create(dev, NULL, &imx8_pcie_phy_ops);
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if (IS_ERR(imx8_phy->phy))
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return PTR_ERR(imx8_phy->phy);
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phy_set_drvdata(imx8_phy->phy, imx8_phy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static struct platform_driver imx8_pcie_phy_driver = {
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.probe = imx8_pcie_phy_probe,
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.driver = {
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.name = "imx8-pcie-phy",
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.of_match_table = imx8_pcie_phy_of_match,
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}
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};
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module_platform_driver(imx8_pcie_phy_driver);
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MODULE_DESCRIPTION("FSL IMX8 PCIE PHY driver");
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MODULE_LICENSE("GPL v2");
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