451 lines
11 KiB
C
451 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017-2020,2022 NXP
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/units.h>
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#define REG_SET 0x4
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#define REG_CLR 0x8
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#define PHY_CTRL 0x0
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#define M_MASK GENMASK(18, 17)
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#define M(n) FIELD_PREP(M_MASK, (n))
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#define CCM_MASK GENMASK(16, 14)
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#define CCM(n) FIELD_PREP(CCM_MASK, (n))
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#define CA_MASK GENMASK(13, 11)
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#define CA(n) FIELD_PREP(CA_MASK, (n))
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#define TST_MASK GENMASK(10, 5)
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#define TST(n) FIELD_PREP(TST_MASK, (n))
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#define CH_EN(id) BIT(3 + (id))
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#define NB BIT(2)
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#define RFB BIT(1)
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#define PD BIT(0)
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/* Power On Reset(POR) value */
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#define CTRL_RESET_VAL (M(0x0) | CCM(0x4) | CA(0x4) | TST(0x25))
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/* PHY initialization value and mask */
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#define CTRL_INIT_MASK (M_MASK | CCM_MASK | CA_MASK | TST_MASK | NB | RFB)
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#define CTRL_INIT_VAL (M(0x0) | CCM(0x5) | CA(0x4) | TST(0x25) | RFB)
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#define PHY_STATUS 0x10
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#define LOCK BIT(0)
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#define PHY_NUM 2
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#define MIN_CLKIN_FREQ (25 * MEGA)
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#define MAX_CLKIN_FREQ (165 * MEGA)
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#define PLL_LOCK_SLEEP 10
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#define PLL_LOCK_TIMEOUT 1000
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struct mixel_lvds_phy {
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struct phy *phy;
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struct phy_configure_opts_lvds cfg;
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unsigned int id;
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};
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struct mixel_lvds_phy_priv {
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struct regmap *regmap;
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struct mutex lock; /* protect remap access and cfg of our own */
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struct clk *phy_ref_clk;
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struct mixel_lvds_phy *phys[PHY_NUM];
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};
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static int mixel_lvds_phy_init(struct phy *phy)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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mutex_lock(&priv->lock);
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regmap_update_bits(priv->regmap,
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PHY_CTRL, CTRL_INIT_MASK, CTRL_INIT_VAL);
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mutex_unlock(&priv->lock);
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return 0;
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}
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static int mixel_lvds_phy_power_on(struct phy *phy)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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struct mixel_lvds_phy *companion = priv->phys[lvds_phy->id ^ 1];
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struct phy_configure_opts_lvds *cfg = &lvds_phy->cfg;
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u32 val = 0;
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u32 locked;
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int ret;
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/* The master PHY would power on the slave PHY. */
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if (cfg->is_slave)
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return 0;
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ret = clk_prepare_enable(priv->phy_ref_clk);
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if (ret < 0) {
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dev_err(&phy->dev,
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"failed to enable PHY reference clock: %d\n", ret);
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return ret;
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}
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mutex_lock(&priv->lock);
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if (cfg->bits_per_lane_and_dclk_cycle == 7) {
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if (cfg->differential_clk_rate < 44000000)
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val |= M(0x2);
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else if (cfg->differential_clk_rate < 90000000)
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val |= M(0x1);
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else
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val |= M(0x0);
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} else {
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val = NB;
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if (cfg->differential_clk_rate < 32000000)
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val |= M(0x2);
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else if (cfg->differential_clk_rate < 63000000)
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val |= M(0x1);
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else
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val |= M(0x0);
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}
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regmap_update_bits(priv->regmap, PHY_CTRL, M_MASK | NB, val);
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/*
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* Enable two channels synchronously,
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* if the companion PHY is a slave PHY.
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*/
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if (companion->cfg.is_slave)
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val = CH_EN(0) | CH_EN(1);
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else
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val = CH_EN(lvds_phy->id);
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regmap_write(priv->regmap, PHY_CTRL + REG_SET, val);
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ret = regmap_read_poll_timeout(priv->regmap, PHY_STATUS, locked,
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locked, PLL_LOCK_SLEEP,
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PLL_LOCK_TIMEOUT);
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if (ret < 0) {
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dev_err(&phy->dev, "failed to get PHY lock: %d\n", ret);
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clk_disable_unprepare(priv->phy_ref_clk);
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}
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mutex_unlock(&priv->lock);
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return ret;
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}
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static int mixel_lvds_phy_power_off(struct phy *phy)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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struct mixel_lvds_phy *companion = priv->phys[lvds_phy->id ^ 1];
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struct phy_configure_opts_lvds *cfg = &lvds_phy->cfg;
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/* The master PHY would power off the slave PHY. */
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if (cfg->is_slave)
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return 0;
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mutex_lock(&priv->lock);
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if (companion->cfg.is_slave)
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regmap_write(priv->regmap, PHY_CTRL + REG_CLR,
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CH_EN(0) | CH_EN(1));
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else
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regmap_write(priv->regmap, PHY_CTRL + REG_CLR,
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CH_EN(lvds_phy->id));
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mutex_unlock(&priv->lock);
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clk_disable_unprepare(priv->phy_ref_clk);
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return 0;
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}
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static int mixel_lvds_phy_configure(struct phy *phy,
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union phy_configure_opts *opts)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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struct phy_configure_opts_lvds *cfg = &opts->lvds;
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int ret;
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ret = clk_set_rate(priv->phy_ref_clk, cfg->differential_clk_rate);
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if (ret)
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dev_err(&phy->dev, "failed to set PHY reference clock rate(%lu): %d\n",
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cfg->differential_clk_rate, ret);
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return ret;
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}
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/* Assume the master PHY's configuration set is cached first. */
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static int mixel_lvds_phy_check_slave(struct phy *slave_phy)
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{
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struct device *dev = &slave_phy->dev;
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev->parent);
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struct mixel_lvds_phy *slv = phy_get_drvdata(slave_phy);
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struct mixel_lvds_phy *mst = priv->phys[slv->id ^ 1];
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struct phy_configure_opts_lvds *mst_cfg = &mst->cfg;
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struct phy_configure_opts_lvds *slv_cfg = &slv->cfg;
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if (mst_cfg->bits_per_lane_and_dclk_cycle !=
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slv_cfg->bits_per_lane_and_dclk_cycle) {
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dev_err(dev, "number bits mismatch(mst: %u vs slv: %u)\n",
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mst_cfg->bits_per_lane_and_dclk_cycle,
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slv_cfg->bits_per_lane_and_dclk_cycle);
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return -EINVAL;
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}
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if (mst_cfg->differential_clk_rate !=
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slv_cfg->differential_clk_rate) {
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dev_err(dev, "dclk rate mismatch(mst: %lu vs slv: %lu)\n",
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mst_cfg->differential_clk_rate,
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slv_cfg->differential_clk_rate);
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return -EINVAL;
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}
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if (mst_cfg->lanes != slv_cfg->lanes) {
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dev_err(dev, "lanes mismatch(mst: %u vs slv: %u)\n",
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mst_cfg->lanes, slv_cfg->lanes);
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return -EINVAL;
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}
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if (mst_cfg->is_slave == slv_cfg->is_slave) {
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dev_err(dev, "master PHY is not found\n");
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return -EINVAL;
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}
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return 0;
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}
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static int mixel_lvds_phy_validate(struct phy *phy, enum phy_mode mode,
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int submode, union phy_configure_opts *opts)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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struct phy_configure_opts_lvds *cfg = &opts->lvds;
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int ret = 0;
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if (mode != PHY_MODE_LVDS) {
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dev_err(&phy->dev, "invalid PHY mode(%d)\n", mode);
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return -EINVAL;
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}
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if (cfg->bits_per_lane_and_dclk_cycle != 7 &&
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cfg->bits_per_lane_and_dclk_cycle != 10) {
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dev_err(&phy->dev, "invalid bits per data lane(%u)\n",
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cfg->bits_per_lane_and_dclk_cycle);
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return -EINVAL;
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}
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if (cfg->lanes != 4 && cfg->lanes != 3) {
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dev_err(&phy->dev, "invalid data lanes(%u)\n", cfg->lanes);
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return -EINVAL;
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}
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if (cfg->differential_clk_rate < MIN_CLKIN_FREQ ||
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cfg->differential_clk_rate > MAX_CLKIN_FREQ) {
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dev_err(&phy->dev, "invalid differential clock rate(%lu)\n",
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cfg->differential_clk_rate);
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return -EINVAL;
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}
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mutex_lock(&priv->lock);
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/* cache configuration set of our own for check */
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memcpy(&lvds_phy->cfg, cfg, sizeof(*cfg));
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if (cfg->is_slave) {
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ret = mixel_lvds_phy_check_slave(phy);
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if (ret)
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dev_err(&phy->dev, "failed to check slave PHY: %d\n", ret);
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}
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mutex_unlock(&priv->lock);
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return ret;
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}
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static const struct phy_ops mixel_lvds_phy_ops = {
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.init = mixel_lvds_phy_init,
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.power_on = mixel_lvds_phy_power_on,
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.power_off = mixel_lvds_phy_power_off,
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.configure = mixel_lvds_phy_configure,
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.validate = mixel_lvds_phy_validate,
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.owner = THIS_MODULE,
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};
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static int mixel_lvds_phy_reset(struct device *dev)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev);
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int ret;
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ret = pm_runtime_resume_and_get(dev);
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if (ret < 0) {
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dev_err(dev, "failed to get PM runtime: %d\n", ret);
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return ret;
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}
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regmap_write(priv->regmap, PHY_CTRL, CTRL_RESET_VAL);
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ret = pm_runtime_put(dev);
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if (ret < 0)
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dev_err(dev, "failed to put PM runtime: %d\n", ret);
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return ret;
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}
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static struct phy *mixel_lvds_phy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev);
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unsigned int phy_id;
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if (args->args_count != 1) {
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dev_err(dev,
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"invalid argument number(%d) for 'phys' property\n",
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args->args_count);
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return ERR_PTR(-EINVAL);
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}
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phy_id = args->args[0];
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if (phy_id >= PHY_NUM) {
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dev_err(dev, "invalid PHY index(%d)\n", phy_id);
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return ERR_PTR(-ENODEV);
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}
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return priv->phys[phy_id]->phy;
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}
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static int mixel_lvds_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy_provider *phy_provider;
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struct mixel_lvds_phy_priv *priv;
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struct mixel_lvds_phy *lvds_phy;
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struct phy *phy;
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int i;
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int ret;
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if (!dev->of_node)
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return -ENODEV;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->regmap = syscon_node_to_regmap(dev->of_node->parent);
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if (IS_ERR(priv->regmap))
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return dev_err_probe(dev, PTR_ERR(priv->regmap),
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"failed to get regmap\n");
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priv->phy_ref_clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->phy_ref_clk))
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return dev_err_probe(dev, PTR_ERR(priv->phy_ref_clk),
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"failed to get PHY reference clock\n");
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mutex_init(&priv->lock);
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dev_set_drvdata(dev, priv);
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pm_runtime_enable(dev);
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ret = mixel_lvds_phy_reset(dev);
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if (ret) {
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dev_err(dev, "failed to do POR reset: %d\n", ret);
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return ret;
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}
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for (i = 0; i < PHY_NUM; i++) {
|
||
|
|
lvds_phy = devm_kzalloc(dev, sizeof(*lvds_phy), GFP_KERNEL);
|
||
|
|
if (!lvds_phy) {
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto err;
|
||
|
|
}
|
||
|
|
|
||
|
|
phy = devm_phy_create(dev, NULL, &mixel_lvds_phy_ops);
|
||
|
|
if (IS_ERR(phy)) {
|
||
|
|
ret = PTR_ERR(phy);
|
||
|
|
dev_err(dev, "failed to create PHY for channel%d: %d\n",
|
||
|
|
i, ret);
|
||
|
|
goto err;
|
||
|
|
}
|
||
|
|
|
||
|
|
lvds_phy->phy = phy;
|
||
|
|
lvds_phy->id = i;
|
||
|
|
priv->phys[i] = lvds_phy;
|
||
|
|
|
||
|
|
phy_set_drvdata(phy, lvds_phy);
|
||
|
|
}
|
||
|
|
|
||
|
|
phy_provider = devm_of_phy_provider_register(dev, mixel_lvds_phy_xlate);
|
||
|
|
if (IS_ERR(phy_provider)) {
|
||
|
|
ret = PTR_ERR(phy_provider);
|
||
|
|
dev_err(dev, "failed to register PHY provider: %d\n", ret);
|
||
|
|
goto err;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
err:
|
||
|
|
pm_runtime_disable(dev);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mixel_lvds_phy_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
pm_runtime_disable(&pdev->dev);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __maybe_unused mixel_lvds_phy_runtime_suspend(struct device *dev)
|
||
|
|
{
|
||
|
|
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev);
|
||
|
|
|
||
|
|
/* power down */
|
||
|
|
mutex_lock(&priv->lock);
|
||
|
|
regmap_write(priv->regmap, PHY_CTRL + REG_SET, PD);
|
||
|
|
mutex_unlock(&priv->lock);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __maybe_unused mixel_lvds_phy_runtime_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev);
|
||
|
|
|
||
|
|
/* power up + control initialization */
|
||
|
|
mutex_lock(&priv->lock);
|
||
|
|
regmap_update_bits(priv->regmap, PHY_CTRL,
|
||
|
|
CTRL_INIT_MASK | PD, CTRL_INIT_VAL);
|
||
|
|
mutex_unlock(&priv->lock);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct dev_pm_ops mixel_lvds_phy_pm_ops = {
|
||
|
|
SET_RUNTIME_PM_OPS(mixel_lvds_phy_runtime_suspend,
|
||
|
|
mixel_lvds_phy_runtime_resume, NULL)
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id mixel_lvds_phy_of_match[] = {
|
||
|
|
{ .compatible = "fsl,imx8qm-lvds-phy" },
|
||
|
|
{ /* sentinel */ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, mixel_lvds_phy_of_match);
|
||
|
|
|
||
|
|
static struct platform_driver mixel_lvds_phy_driver = {
|
||
|
|
.probe = mixel_lvds_phy_probe,
|
||
|
|
.remove = mixel_lvds_phy_remove,
|
||
|
|
.driver = {
|
||
|
|
.pm = &mixel_lvds_phy_pm_ops,
|
||
|
|
.name = "mixel-lvds-phy",
|
||
|
|
.of_match_table = mixel_lvds_phy_of_match,
|
||
|
|
}
|
||
|
|
};
|
||
|
|
module_platform_driver(mixel_lvds_phy_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Mixel LVDS PHY driver");
|
||
|
|
MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
|
||
|
|
MODULE_LICENSE("GPL");
|