124 lines
5.3 KiB
C
124 lines
5.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCIE_QHP_H_
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#define QCOM_PHY_QMP_PCIE_QHP_H_
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/* PCIE GEN3 COM registers */
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#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
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#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
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#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
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#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
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#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
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#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
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#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
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#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
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#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
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#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
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#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70
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#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78
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#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c
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#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98
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#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4
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#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8
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#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0
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#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4
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#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc
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#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0
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#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc
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#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0
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#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8
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#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100
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#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108
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#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c
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#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120
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#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124
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#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128
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#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c
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#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130
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#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150
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#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158
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#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178
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#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8
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#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc
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#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0
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#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0
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#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8
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#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0
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#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc
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#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c
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#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224
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#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228
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#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c
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/* PCIE GEN3 QHP Lane registers */
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#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc
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#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10
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#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14
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#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18
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#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60
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#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64
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#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c
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#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0
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#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4
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#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8
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#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0
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#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4
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#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8
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#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc
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#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0
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#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc
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#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100
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#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108
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#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114
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#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118
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#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c
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#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120
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#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124
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#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128
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#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130
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#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134
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#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138
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#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c
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#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154
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#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160
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#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168
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#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c
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#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178
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#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180
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#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184
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#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188
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#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c
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#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190
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#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194
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#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198
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#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c
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#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4
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#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0
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#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4
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#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8
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#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230
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#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234
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#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238
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#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4
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#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8
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#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac
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#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0
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#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8
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#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0
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#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4
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#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc
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/* PCIE GEN3 PCS registers */
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#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c
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#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40
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#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54
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#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68
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#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c
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#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
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#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
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#endif
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