329 lines
16 KiB
C
329 lines
16 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_
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#define QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_
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/* Only for QMP V5 5NM PHY - TX registers */
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#define QSERDES_V5_5NM_TX_BIST_MODE_LANENO 0x00
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#define QSERDES_V5_5NM_TX_BIST_INVERT 0x04
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#define QSERDES_V5_5NM_TX_CLKBUF_ENABLE 0x08
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#define QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL 0x0c
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#define QSERDES_V5_5NM_TX_TX_IDLE_LVL_LARGE_AMP 0x10
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#define QSERDES_V5_5NM_TX_TX_DRV_LVL 0x14
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#define QSERDES_V5_5NM_TX_TX_DRV_LVL_OFFSET 0x18
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#define QSERDES_V5_5NM_TX_RESET_TSYNC_EN 0x1c
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#define QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN 0x20
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#define QSERDES_V5_5NM_TX_LPB_EN 0x24
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#define QSERDES_V5_5NM_TX_RES_CODE_LANE_TX 0x28
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#define QSERDES_V5_5NM_TX_RES_CODE_LANE_RX 0x2c
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#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX 0x30
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#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX 0x34
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#define QSERDES_V5_5NM_TX_PERL_LENGTH1 0x38
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#define QSERDES_V5_5NM_TX_PERL_LENGTH2 0x3c
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#define QSERDES_V5_5NM_TX_SERDES_BYP_EN_OUT 0x40
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#define QSERDES_V5_5NM_TX_DEBUG_BUS_SEL 0x44
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#define QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN 0x48
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#define QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN 0x4c
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#define QSERDES_V5_5NM_TX_TX_POL_INV 0x50
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#define QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN 0x54
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#define QSERDES_V5_5NM_TX_BIST_PATTERN1 0x58
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#define QSERDES_V5_5NM_TX_BIST_PATTERN2 0x5c
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#define QSERDES_V5_5NM_TX_BIST_PATTERN3 0x60
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#define QSERDES_V5_5NM_TX_BIST_PATTERN4 0x64
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#define QSERDES_V5_5NM_TX_BIST_PATTERN5 0x68
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#define QSERDES_V5_5NM_TX_BIST_PATTERN6 0x6c
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#define QSERDES_V5_5NM_TX_BIST_PATTERN7 0x70
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#define QSERDES_V5_5NM_TX_BIST_PATTERN8 0x74
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#define QSERDES_V5_5NM_TX_LANE_MODE_1 0x78
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#define QSERDES_V5_5NM_TX_LANE_MODE_2 0x7c
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#define QSERDES_V5_5NM_TX_LANE_MODE_3 0x80
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#define QSERDES_V5_5NM_TX_ATB_SEL1 0x84
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#define QSERDES_V5_5NM_TX_ATB_SEL2 0x88
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#define QSERDES_V5_5NM_TX_RCV_DETECT_LVL 0x8c
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#define QSERDES_V5_5NM_TX_RCV_DETECT_LVL_2 0x90
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#define QSERDES_V5_5NM_TX_PRBS_SEED1 0x94
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#define QSERDES_V5_5NM_TX_PRBS_SEED2 0x98
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#define QSERDES_V5_5NM_TX_PRBS_SEED3 0x9c
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#define QSERDES_V5_5NM_TX_PRBS_SEED4 0xa0
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#define QSERDES_V5_5NM_TX_RESET_GEN 0xa4
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#define QSERDES_V5_5NM_TX_RESET_GEN_MUXES 0xa8
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#define QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN 0xac
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#define QSERDES_V5_5NM_TX_VMODE_CTRL1 0xb0
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#define QSERDES_V5_5NM_TX_ALOG_OBSV_BUS_CTRL_1 0xb4
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#define QSERDES_V5_5NM_TX_BIST_STATUS 0xb8
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#define QSERDES_V5_5NM_TX_BIST_ERROR_COUNT1 0xbc
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#define QSERDES_V5_5NM_TX_BIST_ERROR_COUNT2 0xc0
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#define QSERDES_V5_5NM_TX_ALOG_OBSV_BUS_STATUS_1 0xc4
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#define QSERDES_V5_5NM_TX_LANE_DIG_CONFIG 0xc8
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#define QSERDES_V5_5NM_TX_PI_QEC_CTRL 0xcc
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#define QSERDES_V5_5NM_TX_PRE_EMPH 0xd0
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#define QSERDES_V5_5NM_TX_SW_RESET 0xd4
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#define QSERDES_V5_5NM_TX_TX_BAND 0xd8
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#define QSERDES_V5_5NM_TX_SLEW_CNTL0 0xdc
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#define QSERDES_V5_5NM_TX_SLEW_CNTL1 0xe0
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#define QSERDES_V5_5NM_TX_INTERFACE_SELECT 0xe4
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#define QSERDES_V5_5NM_TX_DIG_BKUP_CTRL 0xe8
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#define QSERDES_V5_5NM_TX_DEBUG_BUS0 0xec
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#define QSERDES_V5_5NM_TX_DEBUG_BUS1 0xf0
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#define QSERDES_V5_5NM_TX_DEBUG_BUS2 0xf4
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#define QSERDES_V5_5NM_TX_DEBUG_BUS3 0xf8
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#define QSERDES_V5_5NM_TX_TX_BKUP_RO_BUS 0xfc
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/* Only for QMP V5 5NM PHY - RX registers */
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE0 0x000
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE1 0x004
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x008
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE3 0x00c
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE0 0x010
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE1 0x014
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE2 0x018
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE3 0x01c
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#define QSERDES_V5_5NM_RX_UCDR_SO_SATURATION 0x020
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#define QSERDES_V5_5NM_RX_UCDR_FO_TO_SO_DELAY 0x024
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE0 0x028
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE0 0x02c
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE1 0x030
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE1 0x034
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE2 0x038
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE2 0x03c
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE3 0x040
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#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE3 0x044
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#define QSERDES_V5_5NM_RX_UCDR_PI_CTRL1 0x048
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#define QSERDES_V5_5NM_RX_UCDR_PI_CTRL2 0x04c
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#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE0 0x050
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#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE1 0x054
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#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE2 0x058
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#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE3 0x05c
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#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE0 0x060
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#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE1 0x064
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#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE2 0x068
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#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE3 0x06c
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#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE0 0x070
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#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE1 0x074
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#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE2 0x078
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#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE3 0x07c
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#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE0 0x080
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#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE1 0x084
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#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2 0x088
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#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE3 0x08c
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#define QSERDES_V5_5NM_RX_RXCLK_DIV2_CTRL 0x090
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#define QSERDES_V5_5NM_RX_RX_BAND 0x094
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#define QSERDES_V5_5NM_RX_RX_TERM_BW 0x098
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#define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE0 0x09c
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#define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE1 0x0a0
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#define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2 0x0a4
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#define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE3 0x0a8
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#define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE0 0x0ac
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#define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE1 0x0b0
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#define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2 0x0b4
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#define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE3 0x0b8
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#define QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS 0x0bc
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#define QSERDES_V5_5NM_RX_UCDR_PD_DATA_FILTER_ENABLES 0x0c0
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#define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE0 0x0c4
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#define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE1 0x0c8
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#define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE2 0x0cc
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#define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x0d0
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#define QSERDES_V5_5NM_RX_AUX_CONTROL 0x0d4
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#define QSERDES_V5_5NM_RX_AUXDATA_TB 0x0d8
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#define QSERDES_V5_5NM_RX_RCLK_AUXDATA_SEL 0x0dc
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#define QSERDES_V5_5NM_RX_EOM_CTRL 0x0e0
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#define QSERDES_V5_5NM_RX_AC_JTAG_ENABLE 0x0e4
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#define QSERDES_V5_5NM_RX_AC_JTAG_INITP 0x0e8
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#define QSERDES_V5_5NM_RX_AC_JTAG_INITN 0x0ec
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#define QSERDES_V5_5NM_RX_AC_JTAG_LVL 0x0f0
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#define QSERDES_V5_5NM_RX_AC_JTAG_MODE 0x0f4
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#define QSERDES_V5_5NM_RX_AC_JTAG_RESET 0x0f8
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#define QSERDES_V5_5NM_RX_RX_RCVR_IQ_EN 0x0fc
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#define QSERDES_V5_5NM_RX_RX_Q_EN_RATES 0x100
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#define QSERDES_V5_5NM_RX_RX_IDAC_I0_DC_OFFSETS 0x104
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#define QSERDES_V5_5NM_RX_RX_IDAC_I0BAR_DC_OFFSETS 0x108
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#define QSERDES_V5_5NM_RX_RX_IDAC_I1_DC_OFFSETS 0x10c
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#define QSERDES_V5_5NM_RX_RX_IDAC_I1BAR_DC_OFFSETS 0x110
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#define QSERDES_V5_5NM_RX_RX_IDAC_Q_DC_OFFSETS 0x114
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#define QSERDES_V5_5NM_RX_RX_IDAC_QBAR_DC_OFFSETS 0x118
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#define QSERDES_V5_5NM_RX_RX_IDAC_A_DC_OFFSETS 0x11c
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#define QSERDES_V5_5NM_RX_RX_IDAC_ABAR_DC_OFFSETS 0x120
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#define QSERDES_V5_5NM_RX_RX_IDAC_EN 0x124
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#define QSERDES_V5_5NM_RX_RX_IDAC_ENABLES 0x128
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#define QSERDES_V5_5NM_RX_RX_IDAC_SIGN 0x12c
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#define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE 0x130
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#define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL1 0x134
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#define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2 0x138
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#define QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET 0x13c
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#define QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE 0x140
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#define QSERDES_V5_5NM_RX_RX_HIGHZ_PARRATE 0x144
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#define QSERDES_V5_5NM_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x148
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#define QSERDES_V5_5NM_RX_DFE_1 0x14c
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#define QSERDES_V5_5NM_RX_DFE_2 0x150
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#define QSERDES_V5_5NM_RX_DFE_3 0x154
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#define QSERDES_V5_5NM_RX_DFE_4 0x158
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#define QSERDES_V5_5NM_RX_DFE_TAP3_CTRL 0x15c
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#define QSERDES_V5_5NM_RX_DFE_TAP3_MANVAL_KTAP 0x160
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#define QSERDES_V5_5NM_RX_DFE_TAP4_CTRL 0x164
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#define QSERDES_V5_5NM_RX_DFE_TAP4_MANVAL_KTAP 0x168
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#define QSERDES_V5_5NM_RX_DFE_TAP5_CTRL 0x16c
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#define QSERDES_V5_5NM_RX_DFE_TAP5_MANVAL_KTAP 0x170
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#define QSERDES_V5_5NM_RX_TX_ADPT_CTRL 0x174
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#define QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1 0x178
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#define QSERDES_V5_5NM_RX_DFE_DAC_ENABLE2 0x17c
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#define QSERDES_V5_5NM_RX_TX_ADAPT_PRE_THRESH1 0x180
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#define QSERDES_V5_5NM_RX_TX_ADAPT_PRE_THRESH2 0x184
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#define QSERDES_V5_5NM_RX_TX_ADAPT_POST_THRESH1 0x188
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#define QSERDES_V5_5NM_RX_TX_ADAPT_POST_THRESH2 0x18c
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#define QSERDES_V5_5NM_RX_TX_ADAPT_MAIN_THRESH1 0x190
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#define QSERDES_V5_5NM_RX_TX_ADAPT_MAIN_THRESH2 0x194
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#define QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1 0x198
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#define QSERDES_V5_5NM_RX_VGA_CAL_CNTRL2 0x19c
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#define QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL 0x1a0
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#define QSERDES_V5_5NM_RX_VTHRESH_CAL_CNTRL1 0x1a4
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#define QSERDES_V5_5NM_RX_VTHRESH_CAL_CNTRL2 0x1a8
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#define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE0 0x1ac
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#define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE1 0x1b0
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#define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE2 0x1b4
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#define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE3 0x1b8
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#define QSERDES_V5_5NM_RX_GM_CAL 0x1bc
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#define QSERDES_V5_5NM_RX_RX_VGA_GAIN2_BLK1 0x1c0
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#define QSERDES_V5_5NM_RX_RX_VGA_GAIN2_BLK2 0x1c4
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#define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL2 0x1c8
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#define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL3 0x1cc
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#define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL4 0x1d0
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#define QSERDES_V5_5NM_RX_RX_IDAC_TSETTLE_LOW 0x1d4
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#define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_LSB 0x1d8
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#define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_MSB 0x1dc
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#define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1e0
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#define QSERDES_V5_5NM_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x1e4
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#define QSERDES_V5_5NM_RX_SIGDET_ENABLES 0x1e8
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#define QSERDES_V5_5NM_RX_SIGDET_CNTRL 0x1ec
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#define QSERDES_V5_5NM_RX_SIGDET_LVL 0x1f0
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#define QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL 0x1f4
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#define QSERDES_V5_5NM_RX_CDR_FREEZE_UP_DN 0x1f8
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#define QSERDES_V5_5NM_RX_CDR_RESET_OVERRIDE 0x1fc
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#define QSERDES_V5_5NM_RX_RX_INTERFACE_MODE 0x200
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#define QSERDES_V5_5NM_RX_JITTER_GEN_MODE 0x204
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#define QSERDES_V5_5NM_RX_SJ_AMP1 0x208
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#define QSERDES_V5_5NM_RX_SJ_AMP2 0x20c
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#define QSERDES_V5_5NM_RX_SJ_PER1 0x210
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#define QSERDES_V5_5NM_RX_SJ_PER2 0x214
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#define QSERDES_V5_5NM_RX_PPM_OFFSET1 0x218
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#define QSERDES_V5_5NM_RX_PPM_OFFSET2 0x21c
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#define QSERDES_V5_5NM_RX_SIGN_PPM_PERIOD1 0x220
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#define QSERDES_V5_5NM_RX_SIGN_PPM_PERIOD2 0x224
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0 0x228
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1 0x22c
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2 0x230
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3 0x234
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4 0x238
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5 0x23c
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6 0x240
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7 0x244
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0 0x248
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1 0x24c
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2 0x250
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3 0x254
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4 0x258
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5 0x25c
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6 0x260
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7 0x264
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B0 0x268
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B1 0x26c
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B2 0x270
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B3 0x274
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B4 0x278
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B5 0x27c
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B6 0x280
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#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B7 0x284
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#define QSERDES_V5_5NM_RX_PHPRE_CTRL 0x288
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#define QSERDES_V5_5NM_RX_PHPRE_INITVAL 0x28c
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#define QSERDES_V5_5NM_RX_DFE_EN_TIMER 0x290
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#define QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET 0x294
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#define QSERDES_V5_5NM_RX_DCC_CTRL1 0x298
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#define QSERDES_V5_5NM_RX_DCC_CTRL2 0x29c
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#define QSERDES_V5_5NM_RX_DCC_OFFSET 0x2a0
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#define QSERDES_V5_5NM_RX_DCC_CMUX_POSTCAL_OFFSET 0x2a4
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#define QSERDES_V5_5NM_RX_DCC_CMUX_CAL_CTRL1 0x2a8
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#define QSERDES_V5_5NM_RX_DCC_CMUX_CAL_CTRL2 0x2ac
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#define QSERDES_V5_5NM_RX_ALOG_OBSV_BUS_CTRL_1 0x2b0
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#define QSERDES_V5_5NM_RX_RX_MARG_CTRL1 0x2b4
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#define QSERDES_V5_5NM_RX_RX_MARG_CTRL2 0x2b8
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#define QSERDES_V5_5NM_RX_RX_MARG_CTRL3 0x2bc
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#define QSERDES_V5_5NM_RX_RX_MARG_CTRL_4 0x2c0
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#define QSERDES_V5_5NM_RX_RX_MARG_CFG_RATE_0_1 0x2c4
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#define QSERDES_V5_5NM_RX_RX_MARG_CFG_RATE_2_3 0x2c8
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_CTRL1 0x2cc
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_CTRL2 0x2d0
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH1_RATE210 0x2d4
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH1_RATE3 0x2d8
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH2_RATE210 0x2dc
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH2_RATE3 0x2e0
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH3_RATE210 0x2e4
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH3_RATE3 0x2e8
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH4_RATE210 0x2ec
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH4_RATE3 0x2f0
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH5_RATE210 0x2f4
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH5_RATE3 0x2f8
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH6_RATE210 0x2fc
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH6_RATE3 0x300
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH7_RATE210 0x304
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#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH7_RATE3 0x308
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#define QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE10 0x30c
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#define QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x310
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||
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#define QSERDES_V5_5NM_RX_RX_MARG_VERTICAL_CTRL 0x314
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#define QSERDES_V5_5NM_RX_RX_MARG_VERTICAL_CODE 0x318
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#define QSERDES_V5_5NM_RX_RES_CODE_THRESH_HIGH_AND_BYP 0x31c
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||
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#define QSERDES_V5_5NM_RX_RES_CODE_THRESH_LOW 0x320
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||
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#define QSERDES_V5_5NM_RX_RX_BKUP_CTRL1 0x324
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||
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#define QSERDES_V5_5NM_RX_RX_BKUP_CTRL2 0x328
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||
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#define QSERDES_V5_5NM_RX_RX_BKUP_CTRL3 0x32c
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||
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#define QSERDES_V5_5NM_RX_PI_CTRL1 0x330
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||
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#define QSERDES_V5_5NM_RX_PI_CTRL2 0x334
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||
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#define QSERDES_V5_5NM_RX_PI_QUAD 0x338
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||
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#define QSERDES_V5_5NM_RX_QPI_CTRL1 0x33c
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||
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#define QSERDES_V5_5NM_RX_QPI_CTRL2 0x340
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||
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#define QSERDES_V5_5NM_RX_QPI_QUAD 0x344
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||
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#define QSERDES_V5_5NM_RX_IDATA1 0x348
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||
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#define QSERDES_V5_5NM_RX_IDATA2 0x34c
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||
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#define QSERDES_V5_5NM_RX_IDATA3 0x350
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||
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#define QSERDES_V5_5NM_RX_AC_JTAG_OUTP 0x354
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||
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#define QSERDES_V5_5NM_RX_AC_JTAG_OUTN 0x358
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||
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#define QSERDES_V5_5NM_RX_RX_SIGDET 0x35c
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||
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#define QSERDES_V5_5NM_RX_ALOG_OBSV_BUS_STATUS_1 0x360
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||
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#define QSERDES_V5_5NM_RX_READ_EQCODE 0x364
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||
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#define QSERDES_V5_5NM_RX_READ_OFFSETCODE 0x368
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||
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#define QSERDES_V5_5NM_RX_IA_ERROR_COUNTER_LOW 0x36c
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||
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#define QSERDES_V5_5NM_RX_IA_ERROR_COUNTER_HIGH 0x370
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||
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#define QSERDES_V5_5NM_RX_VGA_READ_CODE 0x374
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||
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#define QSERDES_V5_5NM_RX_VTHRESH_READ_CODE 0x378
|
||
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#define QSERDES_V5_5NM_RX_DFE_TAP1_READ_CODE 0x37c
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||
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#define QSERDES_V5_5NM_RX_DFE_TAP2_READ_CODE 0x380
|
||
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#define QSERDES_V5_5NM_RX_DFE_TAP3_READ_CODE 0x384
|
||
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#define QSERDES_V5_5NM_RX_DFE_TAP4_READ_CODE 0x388
|
||
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#define QSERDES_V5_5NM_RX_DFE_TAP5_READ_CODE 0x38c
|
||
|
|
#define QSERDES_V5_5NM_RX_IDAC_STATUS_I0 0x390
|
||
|
|
#define QSERDES_V5_5NM_RX_IDAC_STATUS_I0BAR 0x394
|
||
|
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#define QSERDES_V5_5NM_RX_IDAC_STATUS_I1 0x398
|
||
|
|
#define QSERDES_V5_5NM_RX_IDAC_STATUS_I1BAR 0x39c
|
||
|
|
#define QSERDES_V5_5NM_RX_IDAC_STATUS_Q 0x3a0
|
||
|
|
#define QSERDES_V5_5NM_RX_IDAC_STATUS_QBAR 0x3a4
|
||
|
|
#define QSERDES_V5_5NM_RX_IDAC_STATUS_A 0x3a8
|
||
|
|
#define QSERDES_V5_5NM_RX_IDAC_STATUS_ABAR 0x3ac
|
||
|
|
#define QSERDES_V5_5NM_RX_IDAC_STATUS_SM_ON 0x3b0
|
||
|
|
#define QSERDES_V5_5NM_RX_IDAC_STATUS_SIGNERROR 0x3b4
|
||
|
|
#define QSERDES_V5_5NM_RX_IVCM_CAL_STATUS 0x3b8
|
||
|
|
#define QSERDES_V5_5NM_RX_IVCM_CAL_DEBUG_STATUS 0x3bc
|
||
|
|
#define QSERDES_V5_5NM_RX_DCC_CAL_STATUS 0x3c0
|
||
|
|
#define QSERDES_V5_5NM_RX_DCC_READ_CODE_STATUS 0x3c4
|
||
|
|
#define QSERDES_V5_5NM_RX_RX_MARG_DEBUG1_STATUS 0x3c8
|
||
|
|
#define QSERDES_V5_5NM_RX_RX_MARG_DEBUG2_STATUS 0x3cc
|
||
|
|
#define QSERDES_V5_5NM_RX_RX_MARG_READ_CODE_STATUS 0x3d0
|
||
|
|
#define QSERDES_V5_5NM_RX_EOM_ERR_CNT_LSB_STATUS 0x3d4
|
||
|
|
#define QSERDES_V5_5NM_RX_EOM_ERR_CNT_MSB_STATUS 0x3d8
|
||
|
|
#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_TUNE_STATUS 0x3dc
|
||
|
|
#define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS1_STATUS 0x3e0
|
||
|
|
#define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS2_STATUS 0x3e4
|
||
|
|
#define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS3_STATUS 0x3e8
|
||
|
|
|
||
|
|
#endif
|