323 lines
8.5 KiB
C
323 lines
8.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Rockchip PCIE3.0 phy driver
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*
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* Copyright (C) 2022 Rockchip Electronics Co., Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/pcie.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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/* Register for RK3568 */
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#define GRF_PCIE30PHY_CON1 0x4
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#define GRF_PCIE30PHY_CON6 0x18
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#define GRF_PCIE30PHY_CON9 0x24
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#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
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#define GRF_PCIE30PHY_STATUS0 0x80
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#define GRF_PCIE30PHY_WR_EN (0xf << 16)
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#define SRAM_INIT_DONE(reg) (reg & BIT(14))
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#define RK3568_BIFURCATION_LANE_0_1 BIT(0)
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/* Register for RK3588 */
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#define PHP_GRF_PCIESEL_CON 0x100
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#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
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#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
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#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
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#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
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#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
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#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
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#define RK3588_LANE_AGGREGATION BIT(2)
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struct rockchip_p3phy_ops;
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struct rockchip_p3phy_priv {
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const struct rockchip_p3phy_ops *ops;
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void __iomem *mmio;
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/* mode: RC, EP */
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int mode;
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/* pcie30_phymode: Aggregation, Bifurcation */
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int pcie30_phymode;
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struct regmap *phy_grf;
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struct regmap *pipe_grf;
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struct reset_control *p30phy;
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struct phy *phy;
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struct clk_bulk_data *clks;
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int num_clks;
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int num_lanes;
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u32 lanes[4];
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};
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struct rockchip_p3phy_ops {
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int (*phy_init)(struct rockchip_p3phy_priv *priv);
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};
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static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
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{
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struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
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/* Actually We don't care EP/RC mode, but just record it */
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switch (submode) {
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case PHY_MODE_PCIE_RC:
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priv->mode = PHY_MODE_PCIE_RC;
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break;
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case PHY_MODE_PCIE_EP:
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priv->mode = PHY_MODE_PCIE_EP;
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break;
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default:
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dev_err(&phy->dev, "%s, invalid mode\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
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{
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struct phy *phy = priv->phy;
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bool bifurcation = false;
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int ret;
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u32 reg;
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/* Deassert PCIe PMA output clamp mode */
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
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for (int i = 0; i < priv->num_lanes; i++) {
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dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
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if (priv->lanes[i] > 1)
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bifurcation = true;
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}
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/* Set bifurcation if needed, and it doesn't care RC/EP */
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if (bifurcation) {
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dev_info(&phy->dev, "bifurcation enabled\n");
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
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GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1);
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
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GRF_PCIE30PHY_DA_OCM);
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} else {
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dev_dbg(&phy->dev, "bifurcation disabled\n");
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
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GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
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}
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reset_control_deassert(priv->p30phy);
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ret = regmap_read_poll_timeout(priv->phy_grf,
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GRF_PCIE30PHY_STATUS0,
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reg, SRAM_INIT_DONE(reg),
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0, 500);
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if (ret)
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dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
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__func__, reg);
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return ret;
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}
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static const struct rockchip_p3phy_ops rk3568_ops = {
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.phy_init = rockchip_p3phy_rk3568_init,
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};
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static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
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{
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u32 reg = 0;
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u8 mode = 0;
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int ret;
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/* Deassert PCIe PMA output clamp mode */
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regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
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/* Set bifurcation if needed */
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for (int i = 0; i < priv->num_lanes; i++) {
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if (!priv->lanes[i])
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mode |= (BIT(i) << 3);
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if (priv->lanes[i] > 1)
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mode |= (BIT(i) >> 1);
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}
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if (!mode)
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reg = RK3588_LANE_AGGREGATION;
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else {
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if (mode & (BIT(0) | BIT(1)))
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reg |= RK3588_BIFURCATION_LANE_0_1;
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if (mode & (BIT(2) | BIT(3)))
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reg |= RK3588_BIFURCATION_LANE_2_3;
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}
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regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
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/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
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if (!IS_ERR(priv->pipe_grf)) {
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reg = (mode & (BIT(6) | BIT(7))) >> 6;
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if (reg)
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regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
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(reg << 16) | reg);
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}
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reset_control_deassert(priv->p30phy);
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ret = regmap_read_poll_timeout(priv->phy_grf,
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RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
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reg, RK3588_SRAM_INIT_DONE(reg),
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0, 500);
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ret |= regmap_read_poll_timeout(priv->phy_grf,
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RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
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reg, RK3588_SRAM_INIT_DONE(reg),
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0, 500);
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if (ret)
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dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n",
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reg);
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return ret;
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}
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static const struct rockchip_p3phy_ops rk3588_ops = {
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.phy_init = rockchip_p3phy_rk3588_init,
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};
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static int rochchip_p3phy_init(struct phy *phy)
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{
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struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
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int ret;
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ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
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if (ret) {
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dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret);
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return ret;
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}
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reset_control_assert(priv->p30phy);
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udelay(1);
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if (priv->ops->phy_init) {
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ret = priv->ops->phy_init(priv);
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if (ret)
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clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
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}
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return ret;
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}
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static int rochchip_p3phy_exit(struct phy *phy)
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{
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struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
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clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
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reset_control_assert(priv->p30phy);
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return 0;
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}
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static const struct phy_ops rochchip_p3phy_ops = {
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.init = rochchip_p3phy_init,
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.exit = rochchip_p3phy_exit,
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.set_mode = rockchip_p3phy_set_mode,
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.owner = THIS_MODULE,
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};
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static int rockchip_p3phy_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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struct rockchip_p3phy_priv *priv;
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struct device_node *np = dev->of_node;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
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if (IS_ERR(priv->mmio)) {
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ret = PTR_ERR(priv->mmio);
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return ret;
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}
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priv->ops = of_device_get_match_data(&pdev->dev);
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if (!priv->ops) {
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dev_err(dev, "no of match data provided\n");
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return -EINVAL;
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}
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priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
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if (IS_ERR(priv->phy_grf)) {
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dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
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return PTR_ERR(priv->phy_grf);
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}
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if (of_device_is_compatible(np, "rockchip,rk3588-pcie3-phy")) {
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priv->pipe_grf =
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syscon_regmap_lookup_by_phandle(dev->of_node,
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"rockchip,pipe-grf");
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if (IS_ERR(priv->pipe_grf))
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dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
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} else {
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priv->pipe_grf = NULL;
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}
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priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes",
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priv->lanes, 2,
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ARRAY_SIZE(priv->lanes));
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/* if no data-lanes assume aggregation */
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if (priv->num_lanes == -EINVAL) {
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dev_dbg(dev, "no data-lanes property found\n");
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priv->num_lanes = 1;
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priv->lanes[0] = 1;
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} else if (priv->num_lanes < 0) {
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dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes);
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return priv->num_lanes;
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}
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priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
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if (IS_ERR(priv->phy)) {
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dev_err(dev, "failed to create combphy\n");
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return PTR_ERR(priv->phy);
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}
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priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy");
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if (IS_ERR(priv->p30phy)) {
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return dev_err_probe(dev, PTR_ERR(priv->p30phy),
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"failed to get phy reset control\n");
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}
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if (!priv->p30phy)
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dev_info(dev, "no phy reset control specified\n");
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priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
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if (priv->num_clks < 1)
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return -ENODEV;
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dev_set_drvdata(dev, priv);
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phy_set_drvdata(priv->phy, priv);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id rockchip_p3phy_of_match[] = {
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{ .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
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{ .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
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{ },
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};
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MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match);
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static struct platform_driver rockchip_p3phy_driver = {
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.probe = rockchip_p3phy_probe,
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.driver = {
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.name = "rockchip-snps-pcie3-phy",
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.of_match_table = rockchip_p3phy_of_match,
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},
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};
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module_platform_driver(rockchip_p3phy_driver);
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MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");
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MODULE_LICENSE("GPL");
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