193 lines
6.2 KiB
C
193 lines
6.2 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Samsung Exynos SoC series PCIe PHY driver
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*
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* Phy provider for PCIe controller on Exynos SoC series
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*
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* Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
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* Jaehoon Chung <jh80.chung@samsung.com>
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*/
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
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/* Sysreg FSYS register offsets and bits for Exynos5433 */
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#define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
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#define PCIE_MAC_RESET_MASK 0xFF
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#define PCIE_MAC_RESET BIT(4)
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#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
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#define PCIE_REFCLK_GATING_EN BIT(0)
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#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
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#define PCIE_PHY_RESET BIT(0)
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#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
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#define PCIE_GLOBAL_RESET BIT(0)
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#define PCIE_REFCLK BIT(1)
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#define PCIE_REFCLK_MASK 0x16
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#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
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/* PMU PCIE PHY isolation control */
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#define EXYNOS5433_PMU_PCIE_PHY_OFFSET 0x730
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/* For Exynos pcie phy */
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struct exynos_pcie_phy {
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void __iomem *base;
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struct regmap *pmureg;
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struct regmap *fsysreg;
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};
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static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
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{
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writel(val, base + offset);
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}
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/* Exynos5433 specific functions */
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static int exynos5433_pcie_phy_init(struct phy *phy)
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{
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struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
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regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
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BIT(0), 1);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
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PCIE_APP_REQ_EXIT_L1_MODE, 0);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
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PCIE_REFCLK_GATING_EN, 0);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
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PCIE_PHY_RESET, 1);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
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PCIE_MAC_RESET, 0);
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/* PHY refclk 24MHz */
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
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PCIE_REFCLK_MASK, PCIE_REFCLK);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
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PCIE_GLOBAL_RESET, 0);
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exynos_pcie_phy_writel(ep->base, 0x11, PCIE_PHY_OFFSET(0x3));
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/* band gap reference on */
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exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x20));
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exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x4b));
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/* jitter tuning */
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exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x4));
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exynos_pcie_phy_writel(ep->base, 0x02, PCIE_PHY_OFFSET(0x7));
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exynos_pcie_phy_writel(ep->base, 0x41, PCIE_PHY_OFFSET(0x21));
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exynos_pcie_phy_writel(ep->base, 0x7F, PCIE_PHY_OFFSET(0x14));
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exynos_pcie_phy_writel(ep->base, 0xC0, PCIE_PHY_OFFSET(0x15));
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exynos_pcie_phy_writel(ep->base, 0x61, PCIE_PHY_OFFSET(0x36));
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/* D0 uninit.. */
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exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x3D));
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/* 24MHz */
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exynos_pcie_phy_writel(ep->base, 0x94, PCIE_PHY_OFFSET(0x8));
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exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x9));
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exynos_pcie_phy_writel(ep->base, 0x93, PCIE_PHY_OFFSET(0xA));
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exynos_pcie_phy_writel(ep->base, 0x6B, PCIE_PHY_OFFSET(0xC));
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exynos_pcie_phy_writel(ep->base, 0xA5, PCIE_PHY_OFFSET(0xF));
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exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x16));
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exynos_pcie_phy_writel(ep->base, 0xA3, PCIE_PHY_OFFSET(0x17));
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exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x1A));
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exynos_pcie_phy_writel(ep->base, 0x71, PCIE_PHY_OFFSET(0x23));
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exynos_pcie_phy_writel(ep->base, 0x4C, PCIE_PHY_OFFSET(0x24));
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exynos_pcie_phy_writel(ep->base, 0x0E, PCIE_PHY_OFFSET(0x26));
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exynos_pcie_phy_writel(ep->base, 0x14, PCIE_PHY_OFFSET(0x7));
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exynos_pcie_phy_writel(ep->base, 0x48, PCIE_PHY_OFFSET(0x43));
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exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x44));
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exynos_pcie_phy_writel(ep->base, 0x03, PCIE_PHY_OFFSET(0x45));
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exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x48));
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exynos_pcie_phy_writel(ep->base, 0x13, PCIE_PHY_OFFSET(0x54));
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exynos_pcie_phy_writel(ep->base, 0x04, PCIE_PHY_OFFSET(0x31));
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exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x32));
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
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PCIE_PHY_RESET, 0);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
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PCIE_MAC_RESET_MASK, PCIE_MAC_RESET);
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return 0;
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}
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static int exynos5433_pcie_phy_exit(struct phy *phy)
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{
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struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
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PCIE_REFCLK_GATING_EN, PCIE_REFCLK_GATING_EN);
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regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
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BIT(0), 0);
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return 0;
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}
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static const struct phy_ops exynos5433_phy_ops = {
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.init = exynos5433_pcie_phy_init,
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.exit = exynos5433_pcie_phy_exit,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id exynos_pcie_phy_match[] = {
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{
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.compatible = "samsung,exynos5433-pcie-phy",
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},
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{},
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};
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static int exynos_pcie_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct exynos_pcie_phy *exynos_phy;
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struct phy *generic_phy;
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struct phy_provider *phy_provider;
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exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
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if (!exynos_phy)
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return -ENOMEM;
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exynos_phy->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(exynos_phy->base))
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return PTR_ERR(exynos_phy->base);
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exynos_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
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"samsung,pmu-syscon");
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if (IS_ERR(exynos_phy->pmureg)) {
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dev_err(&pdev->dev, "PMU regmap lookup failed.\n");
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return PTR_ERR(exynos_phy->pmureg);
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}
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exynos_phy->fsysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
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"samsung,fsys-sysreg");
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if (IS_ERR(exynos_phy->fsysreg)) {
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dev_err(&pdev->dev, "FSYS sysreg regmap lookup failed.\n");
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return PTR_ERR(exynos_phy->fsysreg);
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}
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generic_phy = devm_phy_create(dev, dev->of_node, &exynos5433_phy_ops);
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if (IS_ERR(generic_phy)) {
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dev_err(dev, "failed to create PHY\n");
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return PTR_ERR(generic_phy);
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}
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phy_set_drvdata(generic_phy, exynos_phy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static struct platform_driver exynos_pcie_phy_driver = {
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.probe = exynos_pcie_phy_probe,
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.driver = {
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.of_match_table = exynos_pcie_phy_match,
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.name = "exynos_pcie_phy",
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.suppress_bind_attrs = true,
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}
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};
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builtin_platform_driver(exynos_pcie_phy_driver);
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