335 lines
12 KiB
C
335 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017~2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/pinctrl/pads-imx8qm.h>
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#include <linux/err.h>
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#include <linux/firmware/imx/sci.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/platform_device.h>
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#include "pinctrl-imx.h"
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static const struct pinctrl_pin_desc imx8qm_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(IMX8QM_SIM0_CLK),
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IMX_PINCTRL_PIN(IMX8QM_SIM0_RST),
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IMX_PINCTRL_PIN(IMX8QM_SIM0_IO),
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IMX_PINCTRL_PIN(IMX8QM_SIM0_PD),
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IMX_PINCTRL_PIN(IMX8QM_SIM0_POWER_EN),
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IMX_PINCTRL_PIN(IMX8QM_SIM0_GPIO0_00),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_SIM),
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IMX_PINCTRL_PIN(IMX8QM_M40_I2C0_SCL),
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IMX_PINCTRL_PIN(IMX8QM_M40_I2C0_SDA),
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IMX_PINCTRL_PIN(IMX8QM_M40_GPIO0_00),
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IMX_PINCTRL_PIN(IMX8QM_M40_GPIO0_01),
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IMX_PINCTRL_PIN(IMX8QM_M41_I2C0_SCL),
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IMX_PINCTRL_PIN(IMX8QM_M41_I2C0_SDA),
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IMX_PINCTRL_PIN(IMX8QM_M41_GPIO0_00),
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IMX_PINCTRL_PIN(IMX8QM_M41_GPIO0_01),
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IMX_PINCTRL_PIN(IMX8QM_GPT0_CLK),
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IMX_PINCTRL_PIN(IMX8QM_GPT0_CAPTURE),
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IMX_PINCTRL_PIN(IMX8QM_GPT0_COMPARE),
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IMX_PINCTRL_PIN(IMX8QM_GPT1_CLK),
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IMX_PINCTRL_PIN(IMX8QM_GPT1_CAPTURE),
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IMX_PINCTRL_PIN(IMX8QM_GPT1_COMPARE),
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IMX_PINCTRL_PIN(IMX8QM_UART0_RX),
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IMX_PINCTRL_PIN(IMX8QM_UART0_TX),
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IMX_PINCTRL_PIN(IMX8QM_UART0_RTS_B),
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IMX_PINCTRL_PIN(IMX8QM_UART0_CTS_B),
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IMX_PINCTRL_PIN(IMX8QM_UART1_TX),
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IMX_PINCTRL_PIN(IMX8QM_UART1_RX),
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IMX_PINCTRL_PIN(IMX8QM_UART1_RTS_B),
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IMX_PINCTRL_PIN(IMX8QM_UART1_CTS_B),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
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IMX_PINCTRL_PIN(IMX8QM_SCU_PMIC_MEMC_ON),
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IMX_PINCTRL_PIN(IMX8QM_SCU_WDOG_OUT),
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IMX_PINCTRL_PIN(IMX8QM_PMIC_I2C_SDA),
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IMX_PINCTRL_PIN(IMX8QM_PMIC_I2C_SCL),
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IMX_PINCTRL_PIN(IMX8QM_PMIC_EARLY_WARNING),
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IMX_PINCTRL_PIN(IMX8QM_PMIC_INT_B),
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IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_00),
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IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_01),
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IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_02),
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IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_03),
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IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_04),
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IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_05),
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IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_06),
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IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_07),
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IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE0),
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IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE1),
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IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE2),
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IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE3),
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IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE4),
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IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE5),
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IMX_PINCTRL_PIN(IMX8QM_LVDS0_GPIO00),
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IMX_PINCTRL_PIN(IMX8QM_LVDS0_GPIO01),
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IMX_PINCTRL_PIN(IMX8QM_LVDS0_I2C0_SCL),
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IMX_PINCTRL_PIN(IMX8QM_LVDS0_I2C0_SDA),
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IMX_PINCTRL_PIN(IMX8QM_LVDS0_I2C1_SCL),
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IMX_PINCTRL_PIN(IMX8QM_LVDS0_I2C1_SDA),
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IMX_PINCTRL_PIN(IMX8QM_LVDS1_GPIO00),
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IMX_PINCTRL_PIN(IMX8QM_LVDS1_GPIO01),
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IMX_PINCTRL_PIN(IMX8QM_LVDS1_I2C0_SCL),
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IMX_PINCTRL_PIN(IMX8QM_LVDS1_I2C0_SDA),
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IMX_PINCTRL_PIN(IMX8QM_LVDS1_I2C1_SCL),
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IMX_PINCTRL_PIN(IMX8QM_LVDS1_I2C1_SDA),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI0_I2C0_SCL),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI0_I2C0_SDA),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI0_GPIO0_00),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI0_GPIO0_01),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI1_I2C0_SCL),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI1_I2C0_SDA),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI1_GPIO0_00),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI1_GPIO0_01),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_MCLK_OUT),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_I2C0_SCL),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_I2C0_SDA),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_GPIO0_00),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_GPIO0_01),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_MCLK_OUT),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_GPIO0_00),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_GPIO0_01),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_I2C0_SCL),
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IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_I2C0_SDA),
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IMX_PINCTRL_PIN(IMX8QM_HDMI_TX0_TS_SCL),
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IMX_PINCTRL_PIN(IMX8QM_HDMI_TX0_TS_SDA),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_3V3_HDMIGPIO),
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IMX_PINCTRL_PIN(IMX8QM_ESAI1_FSR),
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IMX_PINCTRL_PIN(IMX8QM_ESAI1_FST),
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IMX_PINCTRL_PIN(IMX8QM_ESAI1_SCKR),
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IMX_PINCTRL_PIN(IMX8QM_ESAI1_SCKT),
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IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX0),
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IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX1),
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IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX2_RX3),
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IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX3_RX2),
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IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX4_RX1),
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IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX5_RX0),
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IMX_PINCTRL_PIN(IMX8QM_SPDIF0_RX),
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IMX_PINCTRL_PIN(IMX8QM_SPDIF0_TX),
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IMX_PINCTRL_PIN(IMX8QM_SPDIF0_EXT_CLK),
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IMX_PINCTRL_PIN(IMX8QM_SPI3_SCK),
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IMX_PINCTRL_PIN(IMX8QM_SPI3_SDO),
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IMX_PINCTRL_PIN(IMX8QM_SPI3_SDI),
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IMX_PINCTRL_PIN(IMX8QM_SPI3_CS0),
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IMX_PINCTRL_PIN(IMX8QM_SPI3_CS1),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
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IMX_PINCTRL_PIN(IMX8QM_ESAI0_FSR),
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IMX_PINCTRL_PIN(IMX8QM_ESAI0_FST),
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IMX_PINCTRL_PIN(IMX8QM_ESAI0_SCKR),
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IMX_PINCTRL_PIN(IMX8QM_ESAI0_SCKT),
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IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX0),
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IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX1),
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IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX2_RX3),
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IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX3_RX2),
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IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX4_RX1),
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IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX5_RX0),
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IMX_PINCTRL_PIN(IMX8QM_MCLK_IN0),
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IMX_PINCTRL_PIN(IMX8QM_MCLK_OUT0),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHC),
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IMX_PINCTRL_PIN(IMX8QM_SPI0_SCK),
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IMX_PINCTRL_PIN(IMX8QM_SPI0_SDO),
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IMX_PINCTRL_PIN(IMX8QM_SPI0_SDI),
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IMX_PINCTRL_PIN(IMX8QM_SPI0_CS0),
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IMX_PINCTRL_PIN(IMX8QM_SPI0_CS1),
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IMX_PINCTRL_PIN(IMX8QM_SPI2_SCK),
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IMX_PINCTRL_PIN(IMX8QM_SPI2_SDO),
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IMX_PINCTRL_PIN(IMX8QM_SPI2_SDI),
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IMX_PINCTRL_PIN(IMX8QM_SPI2_CS0),
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IMX_PINCTRL_PIN(IMX8QM_SPI2_CS1),
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IMX_PINCTRL_PIN(IMX8QM_SAI1_RXC),
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IMX_PINCTRL_PIN(IMX8QM_SAI1_RXD),
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IMX_PINCTRL_PIN(IMX8QM_SAI1_RXFS),
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IMX_PINCTRL_PIN(IMX8QM_SAI1_TXC),
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IMX_PINCTRL_PIN(IMX8QM_SAI1_TXD),
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IMX_PINCTRL_PIN(IMX8QM_SAI1_TXFS),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
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IMX_PINCTRL_PIN(IMX8QM_ADC_IN7),
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IMX_PINCTRL_PIN(IMX8QM_ADC_IN6),
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IMX_PINCTRL_PIN(IMX8QM_ADC_IN5),
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IMX_PINCTRL_PIN(IMX8QM_ADC_IN4),
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IMX_PINCTRL_PIN(IMX8QM_ADC_IN3),
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IMX_PINCTRL_PIN(IMX8QM_ADC_IN2),
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IMX_PINCTRL_PIN(IMX8QM_ADC_IN1),
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IMX_PINCTRL_PIN(IMX8QM_ADC_IN0),
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IMX_PINCTRL_PIN(IMX8QM_MLB_SIG),
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IMX_PINCTRL_PIN(IMX8QM_MLB_CLK),
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IMX_PINCTRL_PIN(IMX8QM_MLB_DATA),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLHT),
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IMX_PINCTRL_PIN(IMX8QM_FLEXCAN0_RX),
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IMX_PINCTRL_PIN(IMX8QM_FLEXCAN0_TX),
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IMX_PINCTRL_PIN(IMX8QM_FLEXCAN1_RX),
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IMX_PINCTRL_PIN(IMX8QM_FLEXCAN1_TX),
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IMX_PINCTRL_PIN(IMX8QM_FLEXCAN2_RX),
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IMX_PINCTRL_PIN(IMX8QM_FLEXCAN2_TX),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOTHR),
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IMX_PINCTRL_PIN(IMX8QM_USB_SS3_TC0),
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IMX_PINCTRL_PIN(IMX8QM_USB_SS3_TC1),
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IMX_PINCTRL_PIN(IMX8QM_USB_SS3_TC2),
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IMX_PINCTRL_PIN(IMX8QM_USB_SS3_TC3),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_3V3_USB3IO),
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IMX_PINCTRL_PIN(IMX8QM_USDHC1_RESET_B),
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IMX_PINCTRL_PIN(IMX8QM_USDHC1_VSELECT),
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IMX_PINCTRL_PIN(IMX8QM_USDHC2_RESET_B),
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IMX_PINCTRL_PIN(IMX8QM_USDHC2_VSELECT),
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IMX_PINCTRL_PIN(IMX8QM_USDHC2_WP),
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IMX_PINCTRL_PIN(IMX8QM_USDHC2_CD_B),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
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IMX_PINCTRL_PIN(IMX8QM_ENET0_MDIO),
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IMX_PINCTRL_PIN(IMX8QM_ENET0_MDC),
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IMX_PINCTRL_PIN(IMX8QM_ENET0_REFCLK_125M_25M),
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IMX_PINCTRL_PIN(IMX8QM_ENET1_REFCLK_125M_25M),
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IMX_PINCTRL_PIN(IMX8QM_ENET1_MDIO),
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IMX_PINCTRL_PIN(IMX8QM_ENET1_MDC),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
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IMX_PINCTRL_PIN(IMX8QM_QSPI1A_SS0_B),
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IMX_PINCTRL_PIN(IMX8QM_QSPI1A_SS1_B),
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IMX_PINCTRL_PIN(IMX8QM_QSPI1A_SCLK),
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IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DQS),
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IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DATA3),
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IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DATA2),
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IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DATA1),
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IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DATA0),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI1),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DATA0),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DATA1),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DATA2),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DATA3),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DQS),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0A_SS0_B),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0A_SS1_B),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0A_SCLK),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0B_SCLK),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DATA0),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DATA1),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DATA2),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DATA3),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DQS),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0B_SS0_B),
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IMX_PINCTRL_PIN(IMX8QM_QSPI0B_SS1_B),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI0),
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IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL0_CLKREQ_B),
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IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL0_WAKE_B),
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IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL0_PERST_B),
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IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL1_CLKREQ_B),
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IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL1_WAKE_B),
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IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL1_PERST_B),
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IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
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IMX_PINCTRL_PIN(IMX8QM_USB_HSIC0_DATA),
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IMX_PINCTRL_PIN(IMX8QM_USB_HSIC0_STROBE),
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IMX_PINCTRL_PIN(IMX8QM_CALIBRATION_0_HSIC),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_CALIBRATION_1_HSIC),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_EMMC0_CLK),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_EMMC0_CMD),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA0),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA1),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA2),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA3),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA4),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA5),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA6),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA7),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_EMMC0_STROBE),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_EMMC0_RESET_B),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_SD1FIX),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC1_CLK),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC1_CMD),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA0),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA1),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_CTL_NAND_RE_P_N),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA2),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA3),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_CTL_NAND_DQS_P_N),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA4),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA5),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA6),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA7),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC1_STROBE),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL2),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC2_CLK),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC2_CMD),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC2_DATA0),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC2_DATA1),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC2_DATA2),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_USDHC2_DATA3),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL3),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXC),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TX_CTL),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXD0),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXD1),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXD2),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXD3),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXC),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RX_CTL),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXD0),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXD1),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXD2),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXD3),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXC),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TX_CTL),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXD0),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXD1),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXD2),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXD3),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXC),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RX_CTL),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXD0),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXD1),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXD2),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXD3),
|
||
|
|
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct imx_pinctrl_soc_info imx8qm_pinctrl_info = {
|
||
|
|
.pins = imx8qm_pinctrl_pads,
|
||
|
|
.npins = ARRAY_SIZE(imx8qm_pinctrl_pads),
|
||
|
|
.flags = IMX_USE_SCU,
|
||
|
|
.imx_pinconf_get = imx_pinconf_get_scu,
|
||
|
|
.imx_pinconf_set = imx_pinconf_set_scu,
|
||
|
|
.imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id imx8qm_pinctrl_of_match[] = {
|
||
|
|
{ .compatible = "fsl,imx8qm-iomuxc", },
|
||
|
|
{ /* sentinel */ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, imx8qm_pinctrl_of_match);
|
||
|
|
|
||
|
|
static int imx8qm_pinctrl_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = imx_pinctrl_sc_ipc_init(pdev);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
return imx_pinctrl_probe(pdev, &imx8qm_pinctrl_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver imx8qm_pinctrl_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "imx8qm-pinctrl",
|
||
|
|
.of_match_table = imx8qm_pinctrl_of_match,
|
||
|
|
.suppress_bind_attrs = true,
|
||
|
|
},
|
||
|
|
.probe = imx8qm_pinctrl_probe,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init imx8qm_pinctrl_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&imx8qm_pinctrl_driver);
|
||
|
|
}
|
||
|
|
arch_initcall(imx8qm_pinctrl_init);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
|
||
|
|
MODULE_DESCRIPTION("NXP i.MX8QM pinctrl driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|