241 lines
8.6 KiB
C
241 lines
8.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/pinctrl/pads-imx8qxp.h>
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#include <linux/err.h>
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#include <linux/firmware/imx/sci.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-imx.h"
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static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_PERST_B),
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IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_CLKREQ_B),
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IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_WAKE_B),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
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IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC0),
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IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC1),
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IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC2),
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IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC3),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO),
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IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CLK),
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IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CMD),
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IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA0),
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IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA1),
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IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA2),
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IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA3),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0),
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IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA4),
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IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA5),
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IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA6),
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IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA7),
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IMX_PINCTRL_PIN(IMX8QXP_EMMC0_STROBE),
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IMX_PINCTRL_PIN(IMX8QXP_EMMC0_RESET_B),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1),
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IMX_PINCTRL_PIN(IMX8QXP_USDHC1_RESET_B),
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IMX_PINCTRL_PIN(IMX8QXP_USDHC1_VSELECT),
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IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_RE_P_N),
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IMX_PINCTRL_PIN(IMX8QXP_USDHC1_WP),
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IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CD_B),
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IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_DQS_P_N),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
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IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CLK),
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IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CMD),
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IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA0),
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IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA1),
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IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA2),
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IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA3),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXC),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TX_CTL),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD0),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD1),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD2),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD3),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXC),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RX_CTL),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD0),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD1),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD2),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD3),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_REFCLK_125M_25M),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDIO),
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IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDC),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
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IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FSR),
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IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FST),
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IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKR),
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IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKT),
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IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX0),
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IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX1),
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IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX2_RX3),
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IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX3_RX2),
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IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX4_RX1),
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IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX5_RX0),
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IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_RX),
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IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_TX),
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IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_EXT_CLK),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
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IMX_PINCTRL_PIN(IMX8QXP_SPI3_SCK),
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IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDO),
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IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDI),
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IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS0),
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IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS1),
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IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN1),
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IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN0),
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IMX_PINCTRL_PIN(IMX8QXP_MCLK_OUT0),
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IMX_PINCTRL_PIN(IMX8QXP_UART1_TX),
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IMX_PINCTRL_PIN(IMX8QXP_UART1_RX),
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IMX_PINCTRL_PIN(IMX8QXP_UART1_RTS_B),
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IMX_PINCTRL_PIN(IMX8QXP_UART1_CTS_B),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK),
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IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXD),
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IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXC),
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IMX_PINCTRL_PIN(IMX8QXP_SAI0_RXD),
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IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXFS),
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IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXD),
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IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXC),
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IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXFS),
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IMX_PINCTRL_PIN(IMX8QXP_SPI2_CS0),
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IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDO),
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IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDI),
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IMX_PINCTRL_PIN(IMX8QXP_SPI2_SCK),
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IMX_PINCTRL_PIN(IMX8QXP_SPI0_SCK),
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IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDI),
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IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDO),
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IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS1),
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IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS0),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
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IMX_PINCTRL_PIN(IMX8QXP_ADC_IN1),
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IMX_PINCTRL_PIN(IMX8QXP_ADC_IN0),
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IMX_PINCTRL_PIN(IMX8QXP_ADC_IN3),
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IMX_PINCTRL_PIN(IMX8QXP_ADC_IN2),
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IMX_PINCTRL_PIN(IMX8QXP_ADC_IN5),
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IMX_PINCTRL_PIN(IMX8QXP_ADC_IN4),
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IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_RX),
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IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_TX),
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IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_RX),
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IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_TX),
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IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_RX),
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IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_TX),
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IMX_PINCTRL_PIN(IMX8QXP_UART0_RX),
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IMX_PINCTRL_PIN(IMX8QXP_UART0_TX),
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IMX_PINCTRL_PIN(IMX8QXP_UART2_TX),
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IMX_PINCTRL_PIN(IMX8QXP_UART2_RX),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SCL),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SDA),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_00),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_01),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SCL),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SDA),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_00),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_01),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO),
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IMX_PINCTRL_PIN(IMX8QXP_JTAG_TRST_B),
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IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SCL),
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IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SDA),
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IMX_PINCTRL_PIN(IMX8QXP_PMIC_INT_B),
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IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_00),
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IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_01),
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IMX_PINCTRL_PIN(IMX8QXP_SCU_PMIC_STANDBY),
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IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE0),
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IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE1),
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IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE2),
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IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE3),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_D00),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_D01),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_D02),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_D03),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_D04),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_D05),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_D06),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_D07),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_HSYNC),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_VSYNC),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_PCLK),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_MCLK),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_EN),
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IMX_PINCTRL_PIN(IMX8QXP_CSI_RESET),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_MCLK_OUT),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SCL),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SDA),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_01),
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IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_00),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA0),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA1),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA2),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA3),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DQS),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS0_B),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS1_B),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SCLK),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SCLK),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA0),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA1),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA2),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA3),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DQS),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS0_B),
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IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS1_B),
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IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B),
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};
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static const struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
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.pins = imx8qxp_pinctrl_pads,
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.npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
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.flags = IMX_USE_SCU,
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.imx_pinconf_get = imx_pinconf_get_scu,
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.imx_pinconf_set = imx_pinconf_set_scu,
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.imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu,
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};
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static const struct of_device_id imx8qxp_pinctrl_of_match[] = {
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{ .compatible = "fsl,imx8qxp-iomuxc", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx8qxp_pinctrl_of_match);
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static int imx8qxp_pinctrl_probe(struct platform_device *pdev)
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{
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int ret;
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ret = imx_pinctrl_sc_ipc_init(pdev);
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if (ret)
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return ret;
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return imx_pinctrl_probe(pdev, &imx8qxp_pinctrl_info);
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}
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static struct platform_driver imx8qxp_pinctrl_driver = {
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.driver = {
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.name = "imx8qxp-pinctrl",
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.of_match_table = imx8qxp_pinctrl_of_match,
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.suppress_bind_attrs = true,
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},
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.probe = imx8qxp_pinctrl_probe,
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};
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static int __init imx8qxp_pinctrl_init(void)
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{
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return platform_driver_register(&imx8qxp_pinctrl_driver);
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}
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arch_initcall(imx8qxp_pinctrl_init);
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MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
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MODULE_DESCRIPTION("NXP i.MX8QXP pinctrl driver");
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MODULE_LICENSE("GPL v2");
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