485 lines
12 KiB
C
485 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020 Linaro Ltd.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/gpio/driver.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/seq_file.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinmux.h>
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#include "../pinctrl-utils.h"
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#include "pinctrl-lpass-lpi.h"
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#define MAX_LPI_NUM_CLKS 2
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struct lpi_pinctrl {
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struct device *dev;
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struct pinctrl_dev *ctrl;
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struct gpio_chip chip;
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struct pinctrl_desc desc;
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char __iomem *tlmm_base;
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char __iomem *slew_base;
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struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
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struct mutex slew_access_lock;
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const struct lpi_pinctrl_variant_data *data;
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};
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static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
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unsigned int addr)
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{
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return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
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}
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static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
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unsigned int addr, unsigned int val)
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{
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iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
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return 0;
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}
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static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
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.get_groups_count = pinctrl_generic_get_group_count,
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.get_group_name = pinctrl_generic_get_group_name,
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.get_group_pins = pinctrl_generic_get_group_pins,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
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.dt_free_map = pinctrl_utils_free_map,
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};
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static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev)
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{
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struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->data->nfunctions;
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}
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static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev,
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unsigned int function)
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{
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struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->data->functions[function].name;
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}
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static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev,
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unsigned int function,
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const char *const **groups,
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unsigned *const num_qgroups)
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{
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struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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*groups = pctrl->data->functions[function].groups;
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*num_qgroups = pctrl->data->functions[function].ngroups;
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return 0;
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}
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static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
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unsigned int group_num)
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{
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struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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const struct lpi_pingroup *g = &pctrl->data->groups[group_num];
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u32 val;
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int i, pin = g->pin;
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for (i = 0; i < g->nfuncs; i++) {
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if (g->funcs[i] == function)
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break;
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}
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if (WARN_ON(i == g->nfuncs))
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return -EINVAL;
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val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
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u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
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lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
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return 0;
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}
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static const struct pinmux_ops lpi_gpio_pinmux_ops = {
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.get_functions_count = lpi_gpio_get_functions_count,
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.get_function_name = lpi_gpio_get_function_name,
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.get_function_groups = lpi_gpio_get_function_groups,
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.set_mux = lpi_gpio_set_mux,
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};
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static int lpi_config_get(struct pinctrl_dev *pctldev,
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unsigned int pin, unsigned long *config)
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{
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unsigned int param = pinconf_to_config_param(*config);
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struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
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unsigned int arg = 0;
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int is_out;
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int pull;
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u32 ctl_reg;
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ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
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is_out = ctl_reg & LPI_GPIO_OE_MASK;
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pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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if (pull == LPI_GPIO_BIAS_DISABLE)
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arg = 1;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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if (pull == LPI_GPIO_PULL_DOWN)
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arg = 1;
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break;
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case PIN_CONFIG_BIAS_BUS_HOLD:
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if (pull == LPI_GPIO_KEEPER)
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arg = 1;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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if (pull == LPI_GPIO_PULL_UP)
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arg = 1;
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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case PIN_CONFIG_OUTPUT:
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if (is_out)
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arg = 1;
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break;
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default:
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return -EINVAL;
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}
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*config = pinconf_to_config_packed(param, arg);
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return 0;
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}
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static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
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unsigned long *configs, unsigned int nconfs)
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{
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struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
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unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
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bool value, output_enabled = false;
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const struct lpi_pingroup *g;
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unsigned long sval;
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int i, slew_offset;
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u32 val;
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g = &pctrl->data->groups[group];
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for (i = 0; i < nconfs; i++) {
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param = pinconf_to_config_param(configs[i]);
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arg = pinconf_to_config_argument(configs[i]);
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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pullup = LPI_GPIO_BIAS_DISABLE;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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pullup = LPI_GPIO_PULL_DOWN;
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break;
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case PIN_CONFIG_BIAS_BUS_HOLD:
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pullup = LPI_GPIO_KEEPER;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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pullup = LPI_GPIO_PULL_UP;
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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output_enabled = false;
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break;
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case PIN_CONFIG_OUTPUT:
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output_enabled = true;
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value = arg;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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strength = arg;
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break;
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case PIN_CONFIG_SLEW_RATE:
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if (arg > LPI_SLEW_RATE_MAX) {
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dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
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arg, group);
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return -EINVAL;
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}
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slew_offset = g->slew_offset;
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if (slew_offset == LPI_NO_SLEW)
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break;
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mutex_lock(&pctrl->slew_access_lock);
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sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
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sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
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sval |= arg << slew_offset;
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iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
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mutex_unlock(&pctrl->slew_access_lock);
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break;
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default:
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return -EINVAL;
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}
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}
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/*
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* As per Hardware Programming Guide, when configuring pin as output,
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* set the pin value before setting output-enable (OE).
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*/
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if (output_enabled) {
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val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
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lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
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}
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val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
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u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
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u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
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LPI_GPIO_OUT_STRENGTH_MASK);
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u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
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lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
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return 0;
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}
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static const struct pinconf_ops lpi_gpio_pinconf_ops = {
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.is_generic = true,
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.pin_config_group_get = lpi_config_get,
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.pin_config_group_set = lpi_config_set,
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};
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static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
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{
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struct lpi_pinctrl *state = gpiochip_get_data(chip);
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unsigned long config;
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config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
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return lpi_config_set(state->ctrl, pin, &config, 1);
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}
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static int lpi_gpio_direction_output(struct gpio_chip *chip,
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unsigned int pin, int val)
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{
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struct lpi_pinctrl *state = gpiochip_get_data(chip);
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unsigned long config;
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config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
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return lpi_config_set(state->ctrl, pin, &config, 1);
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}
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static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
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{
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struct lpi_pinctrl *state = gpiochip_get_data(chip);
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return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &
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LPI_GPIO_VALUE_IN_MASK;
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}
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static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
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{
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struct lpi_pinctrl *state = gpiochip_get_data(chip);
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unsigned long config;
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config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
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lpi_config_set(state->ctrl, pin, &config, 1);
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}
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#ifdef CONFIG_DEBUG_FS
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#include <linux/seq_file.h>
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static unsigned int lpi_regval_to_drive(u32 val)
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{
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return (val + 1) * 2;
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}
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static void lpi_gpio_dbg_show_one(struct seq_file *s,
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struct pinctrl_dev *pctldev,
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struct gpio_chip *chip,
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unsigned int offset,
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unsigned int gpio)
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{
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struct lpi_pinctrl *state = gpiochip_get_data(chip);
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struct pinctrl_pin_desc pindesc;
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unsigned int func;
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int is_out;
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int drive;
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int pull;
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u32 ctl_reg;
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static const char * const pulls[] = {
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"no pull",
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"pull down",
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"keeper",
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"pull up"
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};
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pctldev = pctldev ? : state->ctrl;
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pindesc = pctldev->desc->pins[offset];
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ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);
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is_out = ctl_reg & LPI_GPIO_OE_MASK;
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func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
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drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
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pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
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seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
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seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
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seq_printf(s, " %s", pulls[pull]);
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}
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static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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{
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unsigned int gpio = chip->base;
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unsigned int i;
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for (i = 0; i < chip->ngpio; i++, gpio++) {
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lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio);
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seq_puts(s, "\n");
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}
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}
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#else
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#define lpi_gpio_dbg_show NULL
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#endif
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static const struct gpio_chip lpi_gpio_template = {
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.direction_input = lpi_gpio_direction_input,
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.direction_output = lpi_gpio_direction_output,
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.get = lpi_gpio_get,
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.set = lpi_gpio_set,
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.request = gpiochip_generic_request,
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.free = gpiochip_generic_free,
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.dbg_show = lpi_gpio_dbg_show,
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};
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static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl)
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{
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int i, ret;
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for (i = 0; i < pctrl->data->npins; i++) {
|
||
|
|
const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i;
|
||
|
|
|
||
|
|
ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name,
|
||
|
|
(int *)&pin_info->number, 1, NULL);
|
||
|
|
if (ret < 0)
|
||
|
|
goto err_pinctrl;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_pinctrl:
|
||
|
|
for (; i > 0; i--)
|
||
|
|
pinctrl_generic_remove_group(pctrl->ctrl, i - 1);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int lpi_pinctrl_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
const struct lpi_pinctrl_variant_data *data;
|
||
|
|
struct device *dev = &pdev->dev;
|
||
|
|
struct lpi_pinctrl *pctrl;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
|
||
|
|
if (!pctrl)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, pctrl);
|
||
|
|
|
||
|
|
data = of_device_get_match_data(dev);
|
||
|
|
if (!data)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
pctrl->data = data;
|
||
|
|
pctrl->dev = &pdev->dev;
|
||
|
|
|
||
|
|
pctrl->clks[0].id = "core";
|
||
|
|
pctrl->clks[1].id = "audio";
|
||
|
|
|
||
|
|
pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
|
||
|
|
if (IS_ERR(pctrl->tlmm_base))
|
||
|
|
return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
|
||
|
|
"TLMM resource not provided\n");
|
||
|
|
|
||
|
|
pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
|
||
|
|
if (IS_ERR(pctrl->slew_base))
|
||
|
|
return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
|
||
|
|
"Slew resource not provided\n");
|
||
|
|
|
||
|
|
if (of_property_read_bool(dev->of_node, "qcom,adsp-bypass-mode"))
|
||
|
|
ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
|
||
|
|
else
|
||
|
|
ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
|
||
|
|
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
|
||
|
|
if (ret)
|
||
|
|
return dev_err_probe(dev, ret, "Can't enable clocks\n");
|
||
|
|
|
||
|
|
pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
|
||
|
|
pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
|
||
|
|
pctrl->desc.confops = &lpi_gpio_pinconf_ops;
|
||
|
|
pctrl->desc.owner = THIS_MODULE;
|
||
|
|
pctrl->desc.name = dev_name(dev);
|
||
|
|
pctrl->desc.pins = data->pins;
|
||
|
|
pctrl->desc.npins = data->npins;
|
||
|
|
pctrl->chip = lpi_gpio_template;
|
||
|
|
pctrl->chip.parent = dev;
|
||
|
|
pctrl->chip.base = -1;
|
||
|
|
pctrl->chip.ngpio = data->npins;
|
||
|
|
pctrl->chip.label = dev_name(dev);
|
||
|
|
pctrl->chip.can_sleep = false;
|
||
|
|
|
||
|
|
mutex_init(&pctrl->slew_access_lock);
|
||
|
|
|
||
|
|
pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
|
||
|
|
if (IS_ERR(pctrl->ctrl)) {
|
||
|
|
ret = PTR_ERR(pctrl->ctrl);
|
||
|
|
dev_err(dev, "failed to add pin controller\n");
|
||
|
|
goto err_pinctrl;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = lpi_build_pin_desc_groups(pctrl);
|
||
|
|
if (ret)
|
||
|
|
goto err_pinctrl;
|
||
|
|
|
||
|
|
ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(pctrl->dev, "can't add gpio chip\n");
|
||
|
|
goto err_pinctrl;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_pinctrl:
|
||
|
|
mutex_destroy(&pctrl->slew_access_lock);
|
||
|
|
clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(lpi_pinctrl_probe);
|
||
|
|
|
||
|
|
int lpi_pinctrl_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
|
||
|
|
int i;
|
||
|
|
|
||
|
|
mutex_destroy(&pctrl->slew_access_lock);
|
||
|
|
clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
|
||
|
|
|
||
|
|
for (i = 0; i < pctrl->data->npins; i++)
|
||
|
|
pinctrl_generic_remove_group(pctrl->ctrl, i);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(lpi_pinctrl_remove);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
|
||
|
|
MODULE_LICENSE("GPL");
|