325 lines
7.8 KiB
C
325 lines
7.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* DesignWare PWM Controller driver
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*
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* Copyright (C) 2018-2020 Intel Corporation
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*
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* Author: Felipe Balbi (Intel)
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* Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
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* Author: Raymond Tan <raymond.tan@intel.com>
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*
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* Limitations:
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* - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low
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* periods are one or more input clock periods long.
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*/
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#include <linux/bitops.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pm_runtime.h>
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#include <linux/pwm.h>
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#define DWC_TIM_LD_CNT(n) ((n) * 0x14)
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#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0)
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#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04)
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#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08)
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#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c)
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#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10)
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#define DWC_TIMERS_INT_STS 0xa0
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#define DWC_TIMERS_EOI 0xa4
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#define DWC_TIMERS_RAW_INT_STS 0xa8
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#define DWC_TIMERS_COMP_VERSION 0xac
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#define DWC_TIMERS_TOTAL 8
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#define DWC_CLK_PERIOD_NS 10
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/* Timer Control Register */
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#define DWC_TIM_CTRL_EN BIT(0)
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#define DWC_TIM_CTRL_MODE BIT(1)
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#define DWC_TIM_CTRL_MODE_FREE (0 << 1)
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#define DWC_TIM_CTRL_MODE_USER (1 << 1)
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#define DWC_TIM_CTRL_INT_MASK BIT(2)
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#define DWC_TIM_CTRL_PWM BIT(3)
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struct dwc_pwm_ctx {
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u32 cnt;
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u32 cnt2;
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u32 ctrl;
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};
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struct dwc_pwm {
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struct pwm_chip chip;
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void __iomem *base;
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struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL];
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};
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#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip))
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static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset)
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{
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return readl(dwc->base + offset);
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}
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static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset)
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{
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writel(value, dwc->base + offset);
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}
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static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled)
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{
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u32 reg;
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reg = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm));
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if (enabled)
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reg |= DWC_TIM_CTRL_EN;
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else
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reg &= ~DWC_TIM_CTRL_EN;
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dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm));
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}
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static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc,
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struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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u64 tmp;
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u32 ctrl;
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u32 high;
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u32 low;
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/*
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* Calculate width of low and high period in terms of input clock
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* periods and check are the result within HW limits between 1 and
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* 2^32 periods.
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*/
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tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS);
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if (tmp < 1 || tmp > (1ULL << 32))
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return -ERANGE;
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low = tmp - 1;
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tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle,
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DWC_CLK_PERIOD_NS);
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if (tmp < 1 || tmp > (1ULL << 32))
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return -ERANGE;
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high = tmp - 1;
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/*
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* Specification says timer usage flow is to disable timer, then
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* program it followed by enable. It also says Load Count is loaded
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* into timer after it is enabled - either after a disable or
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* a reset. Based on measurements it happens also without disable
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* whenever Load Count is updated. But follow the specification.
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*/
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__dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
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/*
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* Write Load Count and Load Count 2 registers. Former defines the
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* width of low period and latter the width of high period in terms
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* multiple of input clock periods:
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* Width = ((Count + 1) * input clock period).
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*/
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dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm));
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dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm));
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/*
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* Set user-defined mode, timer reloads from Load Count registers
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* when it counts down to 0.
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* Set PWM mode, it makes output to toggle and width of low and high
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* periods are set by Load Count registers.
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*/
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ctrl = DWC_TIM_CTRL_MODE_USER | DWC_TIM_CTRL_PWM;
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dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm));
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/*
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* Enable timer. Output starts from low period.
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*/
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__dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled);
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return 0;
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}
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static int dwc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct dwc_pwm *dwc = to_dwc_pwm(chip);
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if (state->polarity != PWM_POLARITY_INVERSED)
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return -EINVAL;
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if (state->enabled) {
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if (!pwm->state.enabled)
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pm_runtime_get_sync(chip->dev);
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return __dwc_pwm_configure_timer(dwc, pwm, state);
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} else {
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if (pwm->state.enabled) {
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__dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
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pm_runtime_put_sync(chip->dev);
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}
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}
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return 0;
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}
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static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct dwc_pwm *dwc = to_dwc_pwm(chip);
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u64 duty, period;
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pm_runtime_get_sync(chip->dev);
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state->enabled = !!(dwc_pwm_readl(dwc,
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DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN);
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duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
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duty += 1;
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duty *= DWC_CLK_PERIOD_NS;
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state->duty_cycle = duty;
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period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
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period += 1;
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period *= DWC_CLK_PERIOD_NS;
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period += duty;
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state->period = period;
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state->polarity = PWM_POLARITY_INVERSED;
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pm_runtime_put_sync(chip->dev);
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return 0;
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}
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static const struct pwm_ops dwc_pwm_ops = {
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.apply = dwc_pwm_apply,
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.get_state = dwc_pwm_get_state,
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.owner = THIS_MODULE,
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};
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static struct dwc_pwm *dwc_pwm_alloc(struct device *dev)
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{
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struct dwc_pwm *dwc;
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dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
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if (!dwc)
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return NULL;
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dwc->chip.dev = dev;
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dwc->chip.ops = &dwc_pwm_ops;
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dwc->chip.npwm = DWC_TIMERS_TOTAL;
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dev_set_drvdata(dev, dwc);
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return dwc;
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}
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static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id)
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{
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struct device *dev = &pci->dev;
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struct dwc_pwm *dwc;
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int ret;
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dwc = dwc_pwm_alloc(dev);
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if (!dwc)
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return -ENOMEM;
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ret = pcim_enable_device(pci);
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if (ret) {
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dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret));
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return ret;
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}
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pci_set_master(pci);
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ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci));
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if (ret) {
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dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret));
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return ret;
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}
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dwc->base = pcim_iomap_table(pci)[0];
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if (!dwc->base) {
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dev_err(dev, "Base address missing\n");
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return -ENOMEM;
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}
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ret = devm_pwmchip_add(dev, &dwc->chip);
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if (ret)
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return ret;
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pm_runtime_put(dev);
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pm_runtime_allow(dev);
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return 0;
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}
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static void dwc_pwm_remove(struct pci_dev *pci)
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{
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pm_runtime_forbid(&pci->dev);
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pm_runtime_get_noresume(&pci->dev);
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}
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#ifdef CONFIG_PM_SLEEP
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static int dwc_pwm_suspend(struct device *dev)
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{
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struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
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struct dwc_pwm *dwc = pci_get_drvdata(pdev);
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int i;
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for (i = 0; i < DWC_TIMERS_TOTAL; i++) {
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if (dwc->chip.pwms[i].state.enabled) {
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dev_err(dev, "PWM %u in use by consumer (%s)\n",
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i, dwc->chip.pwms[i].label);
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return -EBUSY;
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}
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dwc->ctx[i].cnt = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i));
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dwc->ctx[i].cnt2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i));
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dwc->ctx[i].ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(i));
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}
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return 0;
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}
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static int dwc_pwm_resume(struct device *dev)
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{
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struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
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struct dwc_pwm *dwc = pci_get_drvdata(pdev);
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int i;
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for (i = 0; i < DWC_TIMERS_TOTAL; i++) {
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dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i));
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dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i));
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dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i));
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}
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume);
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static const struct pci_device_id dwc_pwm_id_table[] = {
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{ PCI_VDEVICE(INTEL, 0x4bb7) }, /* Elkhart Lake */
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{ } /* Terminating Entry */
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};
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MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table);
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static struct pci_driver dwc_pwm_driver = {
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.name = "pwm-dwc",
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.probe = dwc_pwm_probe,
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.remove = dwc_pwm_remove,
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.id_table = dwc_pwm_id_table,
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.driver = {
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.pm = &dwc_pwm_pm_ops,
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},
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};
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module_pci_driver(dwc_pwm_driver);
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MODULE_AUTHOR("Felipe Balbi (Intel)");
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MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
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MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
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MODULE_DESCRIPTION("DesignWare PWM Controller");
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MODULE_LICENSE("GPL");
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