402 lines
12 KiB
C
402 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
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* Copyright (c) 2014- QLogic Corporation.
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* All rights reserved
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* www.qlogic.com
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*
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* Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
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*/
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#include "bfad_drv.h"
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#include "bfa_ioc.h"
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#include "bfi_reg.h"
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#include "bfa_defs.h"
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BFA_TRC_FILE(CNA, IOC_CB);
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#define bfa_ioc_cb_join_pos(__ioc) ((u32) (1 << BFA_IOC_CB_JOIN_SH))
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/*
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* forward declarations
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*/
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static bfa_boolean_t bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix);
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static void bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc);
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static bfa_boolean_t bfa_ioc_cb_sync_start(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc);
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static bfa_boolean_t bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_set_cur_ioc_fwstate(
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struct bfa_ioc_s *ioc, enum bfi_ioc_state fwstate);
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static enum bfi_ioc_state bfa_ioc_cb_get_cur_ioc_fwstate(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_set_alt_ioc_fwstate(
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struct bfa_ioc_s *ioc, enum bfi_ioc_state fwstate);
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static enum bfi_ioc_state bfa_ioc_cb_get_alt_ioc_fwstate(struct bfa_ioc_s *ioc);
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static struct bfa_ioc_hwif_s hwif_cb;
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/*
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* Called from bfa_ioc_attach() to map asic specific calls.
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*/
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void
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bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc)
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{
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hwif_cb.ioc_pll_init = bfa_ioc_cb_pll_init;
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hwif_cb.ioc_firmware_lock = bfa_ioc_cb_firmware_lock;
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hwif_cb.ioc_firmware_unlock = bfa_ioc_cb_firmware_unlock;
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hwif_cb.ioc_reg_init = bfa_ioc_cb_reg_init;
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hwif_cb.ioc_map_port = bfa_ioc_cb_map_port;
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hwif_cb.ioc_isr_mode_set = bfa_ioc_cb_isr_mode_set;
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hwif_cb.ioc_notify_fail = bfa_ioc_cb_notify_fail;
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hwif_cb.ioc_ownership_reset = bfa_ioc_cb_ownership_reset;
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hwif_cb.ioc_sync_start = bfa_ioc_cb_sync_start;
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hwif_cb.ioc_sync_join = bfa_ioc_cb_sync_join;
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hwif_cb.ioc_sync_leave = bfa_ioc_cb_sync_leave;
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hwif_cb.ioc_sync_ack = bfa_ioc_cb_sync_ack;
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hwif_cb.ioc_sync_complete = bfa_ioc_cb_sync_complete;
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hwif_cb.ioc_set_fwstate = bfa_ioc_cb_set_cur_ioc_fwstate;
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hwif_cb.ioc_get_fwstate = bfa_ioc_cb_get_cur_ioc_fwstate;
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hwif_cb.ioc_set_alt_fwstate = bfa_ioc_cb_set_alt_ioc_fwstate;
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hwif_cb.ioc_get_alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate;
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ioc->ioc_hwif = &hwif_cb;
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}
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/*
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* Return true if firmware of current driver matches the running firmware.
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*/
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static bfa_boolean_t
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bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc)
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{
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enum bfi_ioc_state alt_fwstate, cur_fwstate;
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struct bfi_ioc_image_hdr_s fwhdr;
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cur_fwstate = bfa_ioc_cb_get_cur_ioc_fwstate(ioc);
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bfa_trc(ioc, cur_fwstate);
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alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate(ioc);
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bfa_trc(ioc, alt_fwstate);
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/*
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* Uninit implies this is the only driver as of now.
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*/
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if (cur_fwstate == BFI_IOC_UNINIT)
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return BFA_TRUE;
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/*
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* Check if another driver with a different firmware is active
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*/
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bfa_ioc_fwver_get(ioc, &fwhdr);
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if (!bfa_ioc_fwver_cmp(ioc, &fwhdr) &&
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alt_fwstate != BFI_IOC_DISABLED) {
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bfa_trc(ioc, alt_fwstate);
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return BFA_FALSE;
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}
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return BFA_TRUE;
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}
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static void
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bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc)
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{
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}
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/*
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* Notify other functions on HB failure.
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*/
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static void
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bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc)
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{
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writel(~0U, ioc->ioc_regs.err_set);
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readl(ioc->ioc_regs.err_set);
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}
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/*
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* Host to LPU mailbox message addresses
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*/
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static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
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{ HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
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{ HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 }
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};
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/*
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* Host <-> LPU mailbox command/status registers
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*/
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static struct { u32 hfn, lpu; } iocreg_mbcmd[] = {
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{ HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },
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{ HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT }
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};
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static void
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bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc)
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{
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void __iomem *rb;
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int pcifn = bfa_ioc_pcifn(ioc);
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rb = bfa_ioc_bar0(ioc);
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ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
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ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
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ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
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if (ioc->port_id == 0) {
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ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
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ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
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ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
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} else {
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ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
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ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
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ioc->ioc_regs.alt_ioc_fwstate = (rb + BFA_IOC0_STATE_REG);
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}
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/*
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* Host <-> LPU mailbox command/status registers
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*/
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ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn;
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ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu;
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/*
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* PSS control registers
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*/
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ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
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ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
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ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG);
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ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG);
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/*
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* IOC semaphore registers and serialization
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*/
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ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
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ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
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/*
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* sram memory access
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*/
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ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
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ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB;
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/*
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* err set reg : for notification of hb failure
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*/
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ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
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}
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/*
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* Initialize IOC to port mapping.
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*/
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static void
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bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc)
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{
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/*
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* For crossbow, port id is same as pci function.
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*/
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ioc->port_id = bfa_ioc_pcifn(ioc);
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bfa_trc(ioc, ioc->port_id);
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}
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/*
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* Set interrupt mode for a function: INTX or MSIX
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*/
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static void
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bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
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{
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}
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/*
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* Synchronized IOC failure processing routines
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*/
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static bfa_boolean_t
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bfa_ioc_cb_sync_start(struct bfa_ioc_s *ioc)
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{
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u32 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
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/**
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* Driver load time. If the join bit is set,
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* it is due to an unclean exit by the driver for this
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* PCI fn in the previous incarnation. Whoever comes here first
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* should clean it up, no matter which PCI fn.
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*/
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if (ioc_fwstate & BFA_IOC_CB_JOIN_MASK) {
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writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate);
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writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate);
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return BFA_TRUE;
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}
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return bfa_ioc_cb_sync_complete(ioc);
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}
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/*
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* Cleanup hw semaphore and usecnt registers
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*/
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static void
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bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc)
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{
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/*
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* Read the hw sem reg to make sure that it is locked
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* before we clear it. If it is not locked, writing 1
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* will lock it instead of clearing it.
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*/
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readl(ioc->ioc_regs.ioc_sem_reg);
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writel(1, ioc->ioc_regs.ioc_sem_reg);
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}
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/*
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* Synchronized IOC failure processing routines
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*/
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static void
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bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc)
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{
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u32 r32 = readl(ioc->ioc_regs.ioc_fwstate);
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u32 join_pos = bfa_ioc_cb_join_pos(ioc);
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writel((r32 | join_pos), ioc->ioc_regs.ioc_fwstate);
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}
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static void
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bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc)
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{
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u32 r32 = readl(ioc->ioc_regs.ioc_fwstate);
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u32 join_pos = bfa_ioc_cb_join_pos(ioc);
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writel((r32 & ~join_pos), ioc->ioc_regs.ioc_fwstate);
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}
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static void
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bfa_ioc_cb_set_cur_ioc_fwstate(struct bfa_ioc_s *ioc,
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enum bfi_ioc_state fwstate)
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{
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u32 r32 = readl(ioc->ioc_regs.ioc_fwstate);
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writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)),
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ioc->ioc_regs.ioc_fwstate);
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}
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static enum bfi_ioc_state
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bfa_ioc_cb_get_cur_ioc_fwstate(struct bfa_ioc_s *ioc)
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{
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return (enum bfi_ioc_state)(readl(ioc->ioc_regs.ioc_fwstate) &
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BFA_IOC_CB_FWSTATE_MASK);
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}
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static void
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bfa_ioc_cb_set_alt_ioc_fwstate(struct bfa_ioc_s *ioc,
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enum bfi_ioc_state fwstate)
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{
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u32 r32 = readl(ioc->ioc_regs.alt_ioc_fwstate);
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writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)),
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ioc->ioc_regs.alt_ioc_fwstate);
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}
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static enum bfi_ioc_state
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bfa_ioc_cb_get_alt_ioc_fwstate(struct bfa_ioc_s *ioc)
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{
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return (enum bfi_ioc_state)(readl(ioc->ioc_regs.alt_ioc_fwstate) &
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BFA_IOC_CB_FWSTATE_MASK);
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}
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static void
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bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc)
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{
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bfa_ioc_cb_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
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}
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static bfa_boolean_t
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bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc)
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{
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u32 fwstate, alt_fwstate;
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fwstate = bfa_ioc_cb_get_cur_ioc_fwstate(ioc);
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/*
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* At this point, this IOC is hoding the hw sem in the
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* start path (fwcheck) OR in the disable/enable path
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* OR to check if the other IOC has acknowledged failure.
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||
|
|
*
|
||
|
|
* So, this IOC can be in UNINIT, INITING, DISABLED, FAIL
|
||
|
|
* or in MEMTEST states. In a normal scenario, this IOC
|
||
|
|
* can not be in OP state when this function is called.
|
||
|
|
*
|
||
|
|
* However, this IOC could still be in OP state when
|
||
|
|
* the OS driver is starting up, if the OptROM code has
|
||
|
|
* left it in that state.
|
||
|
|
*
|
||
|
|
* If we had marked this IOC's fwstate as BFI_IOC_FAIL
|
||
|
|
* in the failure case and now, if the fwstate is not
|
||
|
|
* BFI_IOC_FAIL it implies that the other PCI fn have
|
||
|
|
* reinitialized the ASIC or this IOC got disabled, so
|
||
|
|
* return TRUE.
|
||
|
|
*/
|
||
|
|
if (fwstate == BFI_IOC_UNINIT ||
|
||
|
|
fwstate == BFI_IOC_INITING ||
|
||
|
|
fwstate == BFI_IOC_DISABLED ||
|
||
|
|
fwstate == BFI_IOC_MEMTEST ||
|
||
|
|
fwstate == BFI_IOC_OP)
|
||
|
|
return BFA_TRUE;
|
||
|
|
else {
|
||
|
|
alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate(ioc);
|
||
|
|
if (alt_fwstate == BFI_IOC_FAIL ||
|
||
|
|
alt_fwstate == BFI_IOC_DISABLED ||
|
||
|
|
alt_fwstate == BFI_IOC_UNINIT ||
|
||
|
|
alt_fwstate == BFI_IOC_INITING ||
|
||
|
|
alt_fwstate == BFI_IOC_MEMTEST)
|
||
|
|
return BFA_TRUE;
|
||
|
|
else
|
||
|
|
return BFA_FALSE;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
bfa_status_t
|
||
|
|
bfa_ioc_cb_pll_init(void __iomem *rb, enum bfi_asic_mode fcmode)
|
||
|
|
{
|
||
|
|
u32 pll_sclk, pll_fclk, join_bits;
|
||
|
|
|
||
|
|
pll_sclk = __APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN |
|
||
|
|
__APP_PLL_SCLK_P0_1(3U) |
|
||
|
|
__APP_PLL_SCLK_JITLMT0_1(3U) |
|
||
|
|
__APP_PLL_SCLK_CNTLMT0_1(3U);
|
||
|
|
pll_fclk = __APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN |
|
||
|
|
__APP_PLL_LCLK_RSEL200500 | __APP_PLL_LCLK_P0_1(3U) |
|
||
|
|
__APP_PLL_LCLK_JITLMT0_1(3U) |
|
||
|
|
__APP_PLL_LCLK_CNTLMT0_1(3U);
|
||
|
|
join_bits = readl(rb + BFA_IOC0_STATE_REG) &
|
||
|
|
BFA_IOC_CB_JOIN_MASK;
|
||
|
|
writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG));
|
||
|
|
join_bits = readl(rb + BFA_IOC1_STATE_REG) &
|
||
|
|
BFA_IOC_CB_JOIN_MASK;
|
||
|
|
writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC1_STATE_REG));
|
||
|
|
writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
|
||
|
|
writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
|
||
|
|
writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
|
||
|
|
writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
|
||
|
|
writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
|
||
|
|
writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
|
||
|
|
writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
|
||
|
|
writel(__APP_PLL_SCLK_BYPASS | __APP_PLL_SCLK_LOGIC_SOFT_RESET,
|
||
|
|
rb + APP_PLL_SCLK_CTL_REG);
|
||
|
|
writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
|
||
|
|
writel(__APP_PLL_LCLK_BYPASS | __APP_PLL_LCLK_LOGIC_SOFT_RESET,
|
||
|
|
rb + APP_PLL_LCLK_CTL_REG);
|
||
|
|
udelay(2);
|
||
|
|
writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
|
||
|
|
writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
|
||
|
|
writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET,
|
||
|
|
rb + APP_PLL_SCLK_CTL_REG);
|
||
|
|
writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET,
|
||
|
|
rb + APP_PLL_LCLK_CTL_REG);
|
||
|
|
udelay(2000);
|
||
|
|
writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
|
||
|
|
writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
|
||
|
|
writel(pll_sclk, (rb + APP_PLL_SCLK_CTL_REG));
|
||
|
|
writel(pll_fclk, (rb + APP_PLL_LCLK_CTL_REG));
|
||
|
|
|
||
|
|
return BFA_STATUS_OK;
|
||
|
|
}
|