72 lines
1.5 KiB
C
72 lines
1.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* Synopsys DesignWare 8250 library header file. */
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#include <linux/io.h>
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#include <linux/notifier.h>
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#include <linux/types.h>
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#include <linux/workqueue.h>
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#include "8250.h"
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struct clk;
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struct reset_control;
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struct dw8250_port_data {
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/* Port properties */
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int line;
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/* DMA operations */
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struct uart_8250_dma dma;
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/* Hardware configuration */
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u8 dlf_size;
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/* RS485 variables */
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bool hw_rs485_support;
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};
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struct dw8250_platform_data {
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u8 usr_reg;
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u32 cpr_val;
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unsigned int quirks;
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};
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struct dw8250_data {
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struct dw8250_port_data data;
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const struct dw8250_platform_data *pdata;
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int msr_mask_on;
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int msr_mask_off;
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struct clk *clk;
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struct clk *pclk;
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struct notifier_block clk_notifier;
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struct work_struct clk_work;
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struct reset_control *rst;
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unsigned int skip_autocfg:1;
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unsigned int uart_16550_compatible:1;
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};
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void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, const struct ktermios *old);
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void dw8250_setup_port(struct uart_port *p);
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static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
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{
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return container_of(data, struct dw8250_data, data);
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}
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static inline u32 dw8250_readl_ext(struct uart_port *p, int offset)
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{
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if (p->iotype == UPIO_MEM32BE)
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return ioread32be(p->membase + offset);
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return readl(p->membase + offset);
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}
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static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
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{
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if (p->iotype == UPIO_MEM32BE)
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iowrite32be(reg, p->membase + offset);
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else
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writel(reg, p->membase + offset);
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}
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