244 lines
6.2 KiB
C
244 lines
6.2 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Intel PXA25x on-chip full speed USB device controller
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*
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* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
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* Copyright (C) 2003 David Brownell
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*/
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#ifndef __LINUX_USB_GADGET_PXA25X_H
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#define __LINUX_USB_GADGET_PXA25X_H
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#include <linux/types.h>
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/*-------------------------------------------------------------------------*/
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/* pxa25x has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */
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#define UFNRH_SIR (1 << 7) /* SOF interrupt request */
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#define UFNRH_SIM (1 << 6) /* SOF interrupt mask */
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#define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */
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#define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */
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#define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */
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/* pxa255 has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */
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#define UDCCFR UDC_RES2 /* UDC Control Function Register */
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#define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */
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#define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */
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/* latest pxa255 errata define new "must be one" bits in UDCCFR */
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#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN|UDCCFR_ACM))
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/*-------------------------------------------------------------------------*/
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struct pxa25x_udc;
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struct pxa25x_ep {
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struct usb_ep ep;
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struct pxa25x_udc *dev;
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struct list_head queue;
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unsigned long pio_irqs;
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unsigned short fifo_size;
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u8 bEndpointAddress;
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u8 bmAttributes;
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unsigned stopped : 1;
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unsigned dma_fixup : 1;
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/* UDCCS = UDC Control/Status for this EP
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* UBCR = UDC Byte Count Remaining (contents of OUT fifo)
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* UDDR = UDC Endpoint Data Register (the fifo)
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* DRCM = DMA Request Channel Map
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*/
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u32 regoff_udccs;
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u32 regoff_ubcr;
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u32 regoff_uddr;
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};
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struct pxa25x_request {
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struct usb_request req;
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struct list_head queue;
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};
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enum ep0_state {
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EP0_IDLE,
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EP0_IN_DATA_PHASE,
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EP0_OUT_DATA_PHASE,
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EP0_END_XFER,
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EP0_STALL,
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};
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#define EP0_FIFO_SIZE ((unsigned)16)
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#define BULK_FIFO_SIZE ((unsigned)64)
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#define ISO_FIFO_SIZE ((unsigned)256)
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#define INT_FIFO_SIZE ((unsigned)8)
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struct udc_stats {
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struct ep0stats {
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unsigned long ops;
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unsigned long bytes;
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} read, write;
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unsigned long irqs;
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};
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#ifdef CONFIG_USB_PXA25X_SMALL
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/* when memory's tight, SMALL config saves code+data. */
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#define PXA_UDC_NUM_ENDPOINTS 3
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#endif
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#ifndef PXA_UDC_NUM_ENDPOINTS
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#define PXA_UDC_NUM_ENDPOINTS 16
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#endif
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struct pxa25x_udc {
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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enum ep0_state ep0state;
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struct udc_stats stats;
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unsigned got_irq : 1,
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vbus : 1,
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pullup : 1,
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has_cfr : 1,
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req_pending : 1,
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req_std : 1,
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req_config : 1,
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suspended : 1,
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active : 1;
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#define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200))
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struct timer_list timer;
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struct device *dev;
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struct clk *clk;
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struct pxa2xx_udc_mach_info *mach;
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struct usb_phy *transceiver;
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u64 dma_mask;
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struct pxa25x_ep ep [PXA_UDC_NUM_ENDPOINTS];
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void __iomem *regs;
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int usb_irq;
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int usb_disc_irq;
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};
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#define to_pxa25x(g) (container_of((g), struct pxa25x_udc, gadget))
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/*-------------------------------------------------------------------------*/
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static struct pxa25x_udc *the_controller;
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/*-------------------------------------------------------------------------*/
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/*
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* Debugging support vanishes in non-debug builds. DBG_NORMAL should be
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* mostly silent during normal use/testing, with no timing side-effects.
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*/
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#define DBG_NORMAL 1 /* error paths, device state transitions */
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#define DBG_VERBOSE 2 /* add some success path trace info */
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#define DBG_NOISY 3 /* ... even more: request level */
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#define DBG_VERY_NOISY 4 /* ... even more: packet level */
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#define DMSG(stuff...) pr_debug("udc: " stuff)
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#ifdef DEBUG
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static const char *state_name[] = {
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"EP0_IDLE",
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"EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
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"EP0_END_XFER", "EP0_STALL"
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};
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#ifdef VERBOSE_DEBUG
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# define UDC_DEBUG DBG_VERBOSE
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#else
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# define UDC_DEBUG DBG_NORMAL
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#endif
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static void __maybe_unused
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dump_udccr(const char *label)
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{
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u32 udccr = UDCCR;
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DMSG("%s %02X =%s%s%s%s%s%s%s%s\n",
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label, udccr,
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(udccr & UDCCR_REM) ? " rem" : "",
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(udccr & UDCCR_RSTIR) ? " rstir" : "",
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(udccr & UDCCR_SRM) ? " srm" : "",
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(udccr & UDCCR_SUSIR) ? " susir" : "",
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(udccr & UDCCR_RESIR) ? " resir" : "",
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(udccr & UDCCR_RSM) ? " rsm" : "",
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(udccr & UDCCR_UDA) ? " uda" : "",
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(udccr & UDCCR_UDE) ? " ude" : "");
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}
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static void __maybe_unused
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dump_udccs0(const char *label)
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{
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u32 udccs0 = UDCCS0;
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DMSG("%s %s %02X =%s%s%s%s%s%s%s%s\n",
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label, state_name[the_controller->ep0state], udccs0,
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(udccs0 & UDCCS0_SA) ? " sa" : "",
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(udccs0 & UDCCS0_RNE) ? " rne" : "",
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(udccs0 & UDCCS0_FST) ? " fst" : "",
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(udccs0 & UDCCS0_SST) ? " sst" : "",
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(udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
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(udccs0 & UDCCS0_FTF) ? " ftf" : "",
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(udccs0 & UDCCS0_IPR) ? " ipr" : "",
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(udccs0 & UDCCS0_OPR) ? " opr" : "");
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}
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static inline u32 udc_ep_get_UDCCS(struct pxa25x_ep *);
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static void __maybe_unused
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dump_state(struct pxa25x_udc *dev)
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{
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u32 tmp;
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unsigned i;
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DMSG("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
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state_name[dev->ep0state],
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UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
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dump_udccr("udccr");
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if (dev->has_cfr) {
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tmp = UDCCFR;
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DMSG("udccfr %02X =%s%s\n", tmp,
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(tmp & UDCCFR_AREN) ? " aren" : "",
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(tmp & UDCCFR_ACM) ? " acm" : "");
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}
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if (!dev->driver) {
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DMSG("no gadget driver bound\n");
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return;
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} else
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DMSG("ep0 driver '%s'\n", dev->driver->driver.name);
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dump_udccs0 ("udccs0");
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DMSG("ep0 IN %lu/%lu, OUT %lu/%lu\n",
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dev->stats.write.bytes, dev->stats.write.ops,
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dev->stats.read.bytes, dev->stats.read.ops);
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for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
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if (dev->ep[i].ep.desc == NULL)
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continue;
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DMSG ("udccs%d = %02x\n", i, udc_ep_get_UDCCS(&dev->ep[i]));
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}
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}
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#else
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#define dump_udccr(x) do{}while(0)
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#define dump_udccs0(x) do{}while(0)
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#define dump_state(x) do{}while(0)
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#define UDC_DEBUG ((unsigned)0)
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#endif
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#define DBG(lvl, stuff...) do{if ((lvl) <= UDC_DEBUG) DMSG(stuff);}while(0)
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#define ERR(stuff...) pr_err("udc: " stuff)
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#define WARNING(stuff...) pr_warn("udc: " stuff)
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#define INFO(stuff...) pr_info("udc: " stuff)
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#endif /* __LINUX_USB_GADGET_PXA25X_H */
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