465 lines
12 KiB
C
465 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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*/
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#include <linux/via-core.h>
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#include <linux/via_i2c.h>
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#include "global.h"
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static void tmds_register_write(int index, u8 data);
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static int tmds_register_read(int index);
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static int tmds_register_read_bytes(int index, u8 *buff, int buff_len);
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static void dvi_get_panel_size_from_DDCv1(
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struct tmds_chip_information *tmds_chip,
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struct tmds_setting_information *tmds_setting);
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static int viafb_dvi_query_EDID(void);
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static inline bool check_tmds_chip(int device_id_subaddr, int device_id)
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{
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return tmds_register_read(device_id_subaddr) == device_id;
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}
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void viafb_init_dvi_size(struct tmds_chip_information *tmds_chip,
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struct tmds_setting_information *tmds_setting)
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{
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DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n");
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viafb_dvi_sense();
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if (viafb_dvi_query_EDID() == 1)
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dvi_get_panel_size_from_DDCv1(tmds_chip, tmds_setting);
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return;
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}
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bool viafb_tmds_trasmitter_identify(void)
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{
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unsigned char sr2a = 0, sr1e = 0, sr3e = 0;
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/* Turn on ouputting pad */
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switch (viaparinfo->chip_info->gfx_chip_name) {
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case UNICHROME_K8M890:
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/*=* DFP Low Pad on *=*/
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sr2a = viafb_read_reg(VIASR, SR2A);
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viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
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break;
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case UNICHROME_P4M900:
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case UNICHROME_P4M890:
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/* DFP Low Pad on */
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sr2a = viafb_read_reg(VIASR, SR2A);
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viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
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/* DVP0 Pad on */
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sr1e = viafb_read_reg(VIASR, SR1E);
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viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
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break;
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default:
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/* DVP0/DVP1 Pad on */
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sr1e = viafb_read_reg(VIASR, SR1E);
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viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
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BIT5 + BIT6 + BIT7);
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/* SR3E[1]Multi-function selection:
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0 = Emulate I2C and DDC bus by GPIO2/3/4. */
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sr3e = viafb_read_reg(VIASR, SR3E);
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viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);
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break;
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}
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/* Check for VT1632: */
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viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = VT1632_TMDS;
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viaparinfo->chip_info->
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tmds_chip_info.tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
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viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_31;
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if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)) {
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/*
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* Currently only support 12bits,dual edge,add 24bits mode later
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*/
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tmds_register_write(0x08, 0x3b);
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DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
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DEBUG_MSG(KERN_INFO "\n %2d",
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viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
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DEBUG_MSG(KERN_INFO "\n %2d",
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viaparinfo->chip_info->tmds_chip_info.i2c_port);
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return true;
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} else {
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viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_2C;
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if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)) {
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tmds_register_write(0x08, 0x3b);
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DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
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DEBUG_MSG(KERN_INFO "\n %2d",
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viaparinfo->chip_info->
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tmds_chip_info.tmds_chip_name);
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DEBUG_MSG(KERN_INFO "\n %2d",
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viaparinfo->chip_info->
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tmds_chip_info.i2c_port);
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return true;
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}
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}
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viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = INTEGRATED_TMDS;
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if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) &&
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((viafb_display_hardware_layout == HW_LAYOUT_DVI_ONLY) ||
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(viafb_display_hardware_layout == HW_LAYOUT_LCD_DVI))) {
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DEBUG_MSG(KERN_INFO "\n Integrated TMDS ! \n");
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return true;
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}
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switch (viaparinfo->chip_info->gfx_chip_name) {
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case UNICHROME_K8M890:
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viafb_write_reg(SR2A, VIASR, sr2a);
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break;
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case UNICHROME_P4M900:
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case UNICHROME_P4M890:
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viafb_write_reg(SR2A, VIASR, sr2a);
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viafb_write_reg(SR1E, VIASR, sr1e);
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break;
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default:
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viafb_write_reg(SR1E, VIASR, sr1e);
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viafb_write_reg(SR3E, VIASR, sr3e);
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break;
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}
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viaparinfo->chip_info->
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tmds_chip_info.tmds_chip_name = NON_TMDS_TRANSMITTER;
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viaparinfo->chip_info->tmds_chip_info.
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tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
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return false;
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}
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static void tmds_register_write(int index, u8 data)
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{
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viafb_i2c_writebyte(viaparinfo->chip_info->tmds_chip_info.i2c_port,
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viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
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index, data);
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}
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static int tmds_register_read(int index)
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{
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u8 data;
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viafb_i2c_readbyte(viaparinfo->chip_info->tmds_chip_info.i2c_port,
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(u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
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(u8) index, &data);
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return data;
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}
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static int tmds_register_read_bytes(int index, u8 *buff, int buff_len)
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{
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viafb_i2c_readbytes(viaparinfo->chip_info->tmds_chip_info.i2c_port,
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(u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
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(u8) index, buff, buff_len);
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return 0;
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}
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/* DVI Set Mode */
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void viafb_dvi_set_mode(const struct fb_var_screeninfo *var,
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u16 cxres, u16 cyres, int iga)
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{
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struct fb_var_screeninfo dvi_var = *var;
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const struct fb_videomode *rb_mode;
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int maxPixelClock;
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maxPixelClock = viaparinfo->shared->tmds_setting_info.max_pixel_clock;
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if (maxPixelClock && PICOS2KHZ(var->pixclock) / 1000 > maxPixelClock) {
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rb_mode = viafb_get_best_rb_mode(var->xres, var->yres, 60);
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if (rb_mode)
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viafb_fill_var_timing_info(&dvi_var, rb_mode);
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}
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viafb_fill_crtc_timing(&dvi_var, cxres, cyres, iga);
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}
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/* Sense DVI Connector */
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int viafb_dvi_sense(void)
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{
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u8 RegSR1E = 0, RegSR3E = 0, RegCR6B = 0, RegCR91 = 0,
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RegCR93 = 0, RegCR9B = 0, data;
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int ret = false;
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DEBUG_MSG(KERN_INFO "viafb_dvi_sense!!\n");
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if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
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/* DI1 Pad on */
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RegSR1E = viafb_read_reg(VIASR, SR1E);
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viafb_write_reg(SR1E, VIASR, RegSR1E | 0x30);
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/* CR6B[0]VCK Input Selection: 1 = External clock. */
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RegCR6B = viafb_read_reg(VIACR, CR6B);
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viafb_write_reg(CR6B, VIACR, RegCR6B | 0x08);
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/* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
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[0] Software Control Power Sequence */
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RegCR91 = viafb_read_reg(VIACR, CR91);
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viafb_write_reg(CR91, VIACR, 0x1D);
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/* CR93[7] DI1 Data Source Selection: 1 = DSP2.
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CR93[5] DI1 Clock Source: 1 = internal.
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CR93[4] DI1 Clock Polarity.
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CR93[3:1] DI1 Clock Adjust. CR93[0] DI1 enable */
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RegCR93 = viafb_read_reg(VIACR, CR93);
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viafb_write_reg(CR93, VIACR, 0x01);
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} else {
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/* DVP0/DVP1 Pad on */
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RegSR1E = viafb_read_reg(VIASR, SR1E);
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viafb_write_reg(SR1E, VIASR, RegSR1E | 0xF0);
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/* SR3E[1]Multi-function selection:
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0 = Emulate I2C and DDC bus by GPIO2/3/4. */
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RegSR3E = viafb_read_reg(VIASR, SR3E);
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viafb_write_reg(SR3E, VIASR, RegSR3E & (~0x20));
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/* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
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[0] Software Control Power Sequence */
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RegCR91 = viafb_read_reg(VIACR, CR91);
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viafb_write_reg(CR91, VIACR, 0x1D);
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/*CR9B[4] DVP1 Data Source Selection: 1 = From secondary
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display.CR9B[2:0] DVP1 Clock Adjust */
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RegCR9B = viafb_read_reg(VIACR, CR9B);
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viafb_write_reg(CR9B, VIACR, 0x01);
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}
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data = (u8) tmds_register_read(0x09);
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if (data & 0x04)
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ret = true;
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if (ret == false) {
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if (viafb_dvi_query_EDID())
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ret = true;
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}
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/* Restore status */
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viafb_write_reg(SR1E, VIASR, RegSR1E);
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viafb_write_reg(CR91, VIACR, RegCR91);
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if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
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viafb_write_reg(CR6B, VIACR, RegCR6B);
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viafb_write_reg(CR93, VIACR, RegCR93);
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} else {
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viafb_write_reg(SR3E, VIASR, RegSR3E);
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viafb_write_reg(CR9B, VIACR, RegCR9B);
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}
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return ret;
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}
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/* Query Flat Panel's EDID Table Version Through DVI Connector */
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static int viafb_dvi_query_EDID(void)
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{
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u8 data0, data1;
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int restore;
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DEBUG_MSG(KERN_INFO "viafb_dvi_query_EDID!!\n");
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restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
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viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0;
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data0 = (u8) tmds_register_read(0x00);
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data1 = (u8) tmds_register_read(0x01);
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if ((data0 == 0) && (data1 == 0xFF)) {
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viaparinfo->chip_info->
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tmds_chip_info.tmds_chip_slave_addr = restore;
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return EDID_VERSION_1; /* Found EDID1 Table */
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}
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return false;
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}
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/* Get Panel Size Using EDID1 Table */
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static void dvi_get_panel_size_from_DDCv1(
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struct tmds_chip_information *tmds_chip,
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struct tmds_setting_information *tmds_setting)
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{
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int i, restore;
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unsigned char EDID_DATA[18];
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DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv1 \n");
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restore = tmds_chip->tmds_chip_slave_addr;
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tmds_chip->tmds_chip_slave_addr = 0xA0;
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for (i = 0x25; i < 0x6D; i++) {
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switch (i) {
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case 0x36:
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case 0x48:
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case 0x5A:
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case 0x6C:
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tmds_register_read_bytes(i, EDID_DATA, 10);
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if (!(EDID_DATA[0] || EDID_DATA[1])) {
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/* The first two byte must be zero. */
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if (EDID_DATA[3] == 0xFD) {
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/* To get max pixel clock. */
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tmds_setting->max_pixel_clock =
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EDID_DATA[9] * 10;
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}
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}
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break;
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default:
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break;
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}
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}
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DEBUG_MSG(KERN_INFO "DVI max pixelclock = %d\n",
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tmds_setting->max_pixel_clock);
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tmds_chip->tmds_chip_slave_addr = restore;
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}
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/* If Disable DVI, turn off pad */
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void viafb_dvi_disable(void)
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{
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if (viaparinfo->chip_info->
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tmds_chip_info.output_interface == INTERFACE_TMDS)
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/* Turn off TMDS power. */
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viafb_write_reg(CRD2, VIACR,
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viafb_read_reg(VIACR, CRD2) | 0x08);
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}
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static void dvi_patch_skew_dvp0(void)
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{
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/* Reset data driving first: */
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viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
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viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
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switch (viaparinfo->chip_info->gfx_chip_name) {
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case UNICHROME_P4M890:
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|
{
|
||
|
|
if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
|
||
|
|
(viaparinfo->tmds_setting_info->v_active ==
|
||
|
|
1200))
|
||
|
|
viafb_write_reg_mask(CR96, VIACR, 0x03,
|
||
|
|
BIT0 + BIT1 + BIT2);
|
||
|
|
else
|
||
|
|
viafb_write_reg_mask(CR96, VIACR, 0x07,
|
||
|
|
BIT0 + BIT1 + BIT2);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
case UNICHROME_P4M900:
|
||
|
|
{
|
||
|
|
viafb_write_reg_mask(CR96, VIACR, 0x07,
|
||
|
|
BIT0 + BIT1 + BIT2 + BIT3);
|
||
|
|
viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
|
||
|
|
viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
default:
|
||
|
|
{
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void dvi_patch_skew_dvp_low(void)
|
||
|
|
{
|
||
|
|
switch (viaparinfo->chip_info->gfx_chip_name) {
|
||
|
|
case UNICHROME_K8M890:
|
||
|
|
{
|
||
|
|
viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
case UNICHROME_P4M900:
|
||
|
|
{
|
||
|
|
viafb_write_reg_mask(CR99, VIACR, 0x08,
|
||
|
|
BIT0 + BIT1 + BIT2 + BIT3);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
case UNICHROME_P4M890:
|
||
|
|
{
|
||
|
|
viafb_write_reg_mask(CR99, VIACR, 0x0F,
|
||
|
|
BIT0 + BIT1 + BIT2 + BIT3);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
default:
|
||
|
|
{
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If Enable DVI, turn off pad */
|
||
|
|
void viafb_dvi_enable(void)
|
||
|
|
{
|
||
|
|
u8 data;
|
||
|
|
|
||
|
|
switch (viaparinfo->chip_info->tmds_chip_info.output_interface) {
|
||
|
|
case INTERFACE_DVP0:
|
||
|
|
viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
|
||
|
|
viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
|
||
|
|
dvi_patch_skew_dvp0();
|
||
|
|
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
|
||
|
|
tmds_register_write(0x88, 0x3b);
|
||
|
|
else
|
||
|
|
/*clear CR91[5] to direct on display period
|
||
|
|
in the secondary diplay path */
|
||
|
|
via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case INTERFACE_DVP1:
|
||
|
|
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
|
||
|
|
viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
|
||
|
|
|
||
|
|
/*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */
|
||
|
|
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
|
||
|
|
tmds_register_write(0x88, 0x3b);
|
||
|
|
else
|
||
|
|
/*clear CR91[5] to direct on display period
|
||
|
|
in the secondary diplay path */
|
||
|
|
via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
|
||
|
|
|
||
|
|
/*fix DVI cannot enable on EPIA-M board */
|
||
|
|
if (viafb_platform_epia_dvi == 1) {
|
||
|
|
viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);
|
||
|
|
viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
|
||
|
|
if (viafb_bus_width == 24) {
|
||
|
|
if (viafb_device_lcd_dualedge == 1)
|
||
|
|
data = 0x3F;
|
||
|
|
else
|
||
|
|
data = 0x37;
|
||
|
|
viafb_i2c_writebyte(viaparinfo->chip_info->
|
||
|
|
tmds_chip_info.i2c_port,
|
||
|
|
viaparinfo->chip_info->
|
||
|
|
tmds_chip_info.tmds_chip_slave_addr,
|
||
|
|
0x08, data);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
case INTERFACE_DFP_HIGH:
|
||
|
|
if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
|
||
|
|
via_write_reg_mask(VIACR, CR97, 0x03, 0x03);
|
||
|
|
|
||
|
|
via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case INTERFACE_DFP_LOW:
|
||
|
|
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
|
||
|
|
break;
|
||
|
|
|
||
|
|
dvi_patch_skew_dvp_low();
|
||
|
|
via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case INTERFACE_TMDS:
|
||
|
|
/* Turn on Display period in the panel path. */
|
||
|
|
viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
|
||
|
|
|
||
|
|
/* Turn on TMDS power. */
|
||
|
|
viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
|
||
|
|
/* Disable LCD Scaling */
|
||
|
|
viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
|
||
|
|
}
|
||
|
|
}
|