184 lines
4.5 KiB
C
184 lines
4.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Author: Andrzej Hajda <a.hajda@samsung.com>
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*
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* Device Tree binding constants for Exynos5250 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
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/* core clocks */
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#define CLK_FIN_PLL 1
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#define CLK_FOUT_APLL 2
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#define CLK_FOUT_MPLL 3
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#define CLK_FOUT_BPLL 4
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#define CLK_FOUT_GPLL 5
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#define CLK_FOUT_CPLL 6
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#define CLK_FOUT_EPLL 7
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#define CLK_FOUT_VPLL 8
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#define CLK_ARM_CLK 9
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#define CLK_DIV_ARM2 10
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/* gate for special clocks (sclk) */
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#define CLK_SCLK_CAM_BAYER 128
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#define CLK_SCLK_CAM0 129
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#define CLK_SCLK_CAM1 130
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#define CLK_SCLK_GSCL_WA 131
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#define CLK_SCLK_GSCL_WB 132
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#define CLK_SCLK_FIMD1 133
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#define CLK_SCLK_MIPI1 134
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#define CLK_SCLK_DP 135
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#define CLK_SCLK_HDMI 136
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#define CLK_SCLK_PIXEL 137
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#define CLK_SCLK_AUDIO0 138
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#define CLK_SCLK_MMC0 139
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#define CLK_SCLK_MMC1 140
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#define CLK_SCLK_MMC2 141
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#define CLK_SCLK_MMC3 142
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#define CLK_SCLK_SATA 143
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#define CLK_SCLK_USB3 144
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#define CLK_SCLK_JPEG 145
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#define CLK_SCLK_UART0 146
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#define CLK_SCLK_UART1 147
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#define CLK_SCLK_UART2 148
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#define CLK_SCLK_UART3 149
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#define CLK_SCLK_PWM 150
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#define CLK_SCLK_AUDIO1 151
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#define CLK_SCLK_AUDIO2 152
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#define CLK_SCLK_SPDIF 153
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#define CLK_SCLK_SPI0 154
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#define CLK_SCLK_SPI1 155
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#define CLK_SCLK_SPI2 156
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#define CLK_DIV_I2S1 157
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#define CLK_DIV_I2S2 158
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#define CLK_SCLK_HDMIPHY 159
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#define CLK_DIV_PCM0 160
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/* gate clocks */
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#define CLK_GSCL0 256
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#define CLK_GSCL1 257
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#define CLK_GSCL2 258
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#define CLK_GSCL3 259
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#define CLK_GSCL_WA 260
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#define CLK_GSCL_WB 261
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#define CLK_SMMU_GSCL0 262
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#define CLK_SMMU_GSCL1 263
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#define CLK_SMMU_GSCL2 264
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#define CLK_SMMU_GSCL3 265
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#define CLK_MFC 266
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#define CLK_SMMU_MFCL 267
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#define CLK_SMMU_MFCR 268
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#define CLK_ROTATOR 269
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#define CLK_JPEG 270
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#define CLK_MDMA1 271
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#define CLK_SMMU_ROTATOR 272
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#define CLK_SMMU_JPEG 273
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#define CLK_SMMU_MDMA1 274
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#define CLK_PDMA0 275
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#define CLK_PDMA1 276
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#define CLK_SATA 277
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#define CLK_USBOTG 278
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#define CLK_MIPI_HSI 279
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#define CLK_SDMMC0 280
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#define CLK_SDMMC1 281
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#define CLK_SDMMC2 282
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#define CLK_SDMMC3 283
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#define CLK_SROMC 284
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#define CLK_USB2 285
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#define CLK_USB3 286
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#define CLK_SATA_PHYCTRL 287
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#define CLK_SATA_PHYI2C 288
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#define CLK_UART0 289
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#define CLK_UART1 290
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#define CLK_UART2 291
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#define CLK_UART3 292
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#define CLK_UART4 293
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#define CLK_I2C0 294
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#define CLK_I2C1 295
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#define CLK_I2C2 296
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#define CLK_I2C3 297
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#define CLK_I2C4 298
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#define CLK_I2C5 299
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#define CLK_I2C6 300
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#define CLK_I2C7 301
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#define CLK_I2C_HDMI 302
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#define CLK_ADC 303
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#define CLK_SPI0 304
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#define CLK_SPI1 305
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#define CLK_SPI2 306
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#define CLK_I2S1 307
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#define CLK_I2S2 308
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#define CLK_PCM1 309
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#define CLK_PCM2 310
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#define CLK_PWM 311
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#define CLK_SPDIF 312
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#define CLK_AC97 313
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#define CLK_HSI2C0 314
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#define CLK_HSI2C1 315
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#define CLK_HSI2C2 316
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#define CLK_HSI2C3 317
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#define CLK_CHIPID 318
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#define CLK_SYSREG 319
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#define CLK_PMU 320
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#define CLK_CMU_TOP 321
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#define CLK_CMU_CORE 322
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#define CLK_CMU_MEM 323
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#define CLK_TZPC0 324
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#define CLK_TZPC1 325
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#define CLK_TZPC2 326
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#define CLK_TZPC3 327
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#define CLK_TZPC4 328
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#define CLK_TZPC5 329
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#define CLK_TZPC6 330
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#define CLK_TZPC7 331
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#define CLK_TZPC8 332
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#define CLK_TZPC9 333
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#define CLK_HDMI_CEC 334
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#define CLK_MCT 335
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#define CLK_WDT 336
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#define CLK_RTC 337
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#define CLK_TMU 338
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#define CLK_FIMD1 339
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#define CLK_MIE1 340
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#define CLK_DSIM0 341
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#define CLK_DP 342
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#define CLK_MIXER 343
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#define CLK_HDMI 344
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#define CLK_G2D 345
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#define CLK_MDMA0 346
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#define CLK_SMMU_MDMA0 347
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#define CLK_SSS 348
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#define CLK_G3D 349
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#define CLK_SMMU_TV 350
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#define CLK_SMMU_FIMD1 351
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#define CLK_SMMU_2D 352
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#define CLK_SMMU_FIMC_ISP 353
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#define CLK_SMMU_FIMC_DRC 354
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#define CLK_SMMU_FIMC_SCC 355
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#define CLK_SMMU_FIMC_SCP 356
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#define CLK_SMMU_FIMC_FD 357
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#define CLK_SMMU_FIMC_MCU 358
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#define CLK_SMMU_FIMC_ODC 359
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#define CLK_SMMU_FIMC_DIS0 360
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#define CLK_SMMU_FIMC_DIS1 361
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#define CLK_SMMU_FIMC_3DNR 362
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#define CLK_SMMU_FIMC_LITE0 363
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#define CLK_SMMU_FIMC_LITE1 364
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#define CLK_CAMIF_TOP 365
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/* mux clocks */
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#define CLK_MOUT_HDMI 1024
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#define CLK_MOUT_GPLL 1025
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#define CLK_MOUT_ACLK200_DISP1_SUB 1026
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#define CLK_MOUT_ACLK300_DISP1_SUB 1027
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#define CLK_MOUT_APLL 1028
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#define CLK_MOUT_MPLL 1029
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#define CLK_MOUT_VPLLSRC 1030
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/* must be greater than maximal clock id */
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#define CLK_NR_CLKS 1031
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
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