176 lines
4.0 KiB
C
176 lines
4.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
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*
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* Device Tree binding constants for Samsung S3C64xx clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
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#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
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/*
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* Let each exported clock get a unique index, which is used on DT-enabled
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* platforms to lookup the clock from a clock specifier. These indices are
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* therefore considered an ABI and so must not be changed. This implies
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* that new clocks should be added either in free spaces between clock groups
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* or at the end.
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*/
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/* Core clocks. */
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#define CLK27M 1
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#define CLK48M 2
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#define FOUT_APLL 3
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#define FOUT_MPLL 4
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#define FOUT_EPLL 5
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#define ARMCLK 6
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#define HCLKX2 7
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#define HCLK 8
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#define PCLK 9
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/* HCLK bus clocks. */
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#define HCLK_3DSE 16
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#define HCLK_UHOST 17
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#define HCLK_SECUR 18
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#define HCLK_SDMA1 19
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#define HCLK_SDMA0 20
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#define HCLK_IROM 21
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#define HCLK_DDR1 22
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#define HCLK_MEM1 23
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#define HCLK_MEM0 24
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#define HCLK_USB 25
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#define HCLK_HSMMC2 26
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#define HCLK_HSMMC1 27
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#define HCLK_HSMMC0 28
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#define HCLK_MDP 29
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#define HCLK_DHOST 30
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#define HCLK_IHOST 31
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#define HCLK_DMA1 32
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#define HCLK_DMA0 33
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#define HCLK_JPEG 34
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#define HCLK_CAMIF 35
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#define HCLK_SCALER 36
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#define HCLK_2D 37
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#define HCLK_TV 38
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#define HCLK_POST0 39
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#define HCLK_ROT 40
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#define HCLK_LCD 41
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#define HCLK_TZIC 42
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#define HCLK_INTC 43
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#define HCLK_MFC 44
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#define HCLK_DDR0 45
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/* PCLK bus clocks. */
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#define PCLK_IIC1 48
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#define PCLK_IIS2 49
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#define PCLK_SKEY 50
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#define PCLK_CHIPID 51
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#define PCLK_SPI1 52
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#define PCLK_SPI0 53
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#define PCLK_HSIRX 54
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#define PCLK_HSITX 55
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#define PCLK_GPIO 56
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#define PCLK_IIC0 57
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#define PCLK_IIS1 58
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#define PCLK_IIS0 59
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#define PCLK_AC97 60
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#define PCLK_TZPC 61
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#define PCLK_TSADC 62
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#define PCLK_KEYPAD 63
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#define PCLK_IRDA 64
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#define PCLK_PCM1 65
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#define PCLK_PCM0 66
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#define PCLK_PWM 67
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#define PCLK_RTC 68
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#define PCLK_WDT 69
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#define PCLK_UART3 70
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#define PCLK_UART2 71
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#define PCLK_UART1 72
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#define PCLK_UART0 73
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#define PCLK_MFC 74
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/* Special clocks. */
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#define SCLK_UHOST 80
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#define SCLK_MMC2_48 81
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#define SCLK_MMC1_48 82
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#define SCLK_MMC0_48 83
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#define SCLK_MMC2 84
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#define SCLK_MMC1 85
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#define SCLK_MMC0 86
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#define SCLK_SPI1_48 87
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#define SCLK_SPI0_48 88
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#define SCLK_SPI1 89
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#define SCLK_SPI0 90
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#define SCLK_DAC27 91
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#define SCLK_TV27 92
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#define SCLK_SCALER27 93
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#define SCLK_SCALER 94
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#define SCLK_LCD27 95
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#define SCLK_LCD 96
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#define SCLK_FIMC 97
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#define SCLK_POST0_27 98
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#define SCLK_AUDIO2 99
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#define SCLK_POST0 100
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#define SCLK_AUDIO1 101
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#define SCLK_AUDIO0 102
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#define SCLK_SECUR 103
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#define SCLK_IRDA 104
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#define SCLK_UART 105
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#define SCLK_MFC 106
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#define SCLK_CAM 107
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#define SCLK_JPEG 108
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#define SCLK_ONENAND 109
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/* MEM0 bus clocks - S3C6410-specific. */
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#define MEM0_CFCON 112
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#define MEM0_ONENAND1 113
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#define MEM0_ONENAND0 114
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#define MEM0_NFCON 115
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#define MEM0_SROM 116
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/* Muxes. */
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#define MOUT_APLL 128
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#define MOUT_MPLL 129
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#define MOUT_EPLL 130
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#define MOUT_MFC 131
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#define MOUT_AUDIO0 132
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#define MOUT_AUDIO1 133
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#define MOUT_UART 134
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#define MOUT_SPI0 135
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#define MOUT_SPI1 136
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#define MOUT_MMC0 137
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#define MOUT_MMC1 138
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#define MOUT_MMC2 139
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#define MOUT_UHOST 140
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#define MOUT_IRDA 141
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#define MOUT_LCD 142
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#define MOUT_SCALER 143
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#define MOUT_DAC27 144
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#define MOUT_TV27 145
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#define MOUT_AUDIO2 146
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/* Dividers. */
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#define DOUT_MPLL 160
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#define DOUT_SECUR 161
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#define DOUT_CAM 162
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#define DOUT_JPEG 163
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#define DOUT_MFC 164
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#define DOUT_MMC0 165
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#define DOUT_MMC1 166
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#define DOUT_MMC2 167
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#define DOUT_LCD 168
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#define DOUT_SCALER 169
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#define DOUT_UHOST 170
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#define DOUT_SPI0 171
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#define DOUT_SPI1 172
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#define DOUT_AUDIO0 173
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#define DOUT_AUDIO1 174
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#define DOUT_UART 175
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#define DOUT_IRDA 176
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#define DOUT_FIMC 177
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#define DOUT_AUDIO2 178
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/* Total number of clocks. */
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#define NR_CLKS (DOUT_AUDIO2 + 1)
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#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */
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