232 lines
6.2 KiB
C
232 lines
6.2 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H
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/* aggre1_noc */
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#define MASTER_QUP_3 0
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#define MASTER_EMAC 1
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#define MASTER_EMAC_1 2
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#define MASTER_SDC 3
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#define MASTER_UFS_MEM 4
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#define MASTER_USB2 5
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#define MASTER_USB3_0 6
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#define MASTER_USB3_1 7
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#define SLAVE_A1NOC_SNOC 8
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/* aggre2_noc */
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#define MASTER_QDSS_BAM 0
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#define MASTER_QUP_0 1
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#define MASTER_QUP_1 2
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#define MASTER_QUP_2 3
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#define MASTER_CNOC_A2NOC 4
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#define MASTER_CRYPTO_CORE0 5
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#define MASTER_CRYPTO_CORE1 6
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#define MASTER_IPA 7
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#define MASTER_QDSS_ETR_0 8
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#define MASTER_QDSS_ETR_1 9
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#define MASTER_UFS_CARD 10
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#define SLAVE_A2NOC_SNOC 11
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/* clk_virt */
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#define MASTER_QUP_CORE_0 0
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#define MASTER_QUP_CORE_1 1
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#define MASTER_QUP_CORE_2 2
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#define MASTER_QUP_CORE_3 3
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#define SLAVE_QUP_CORE_0 4
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#define SLAVE_QUP_CORE_1 5
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#define SLAVE_QUP_CORE_2 6
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#define SLAVE_QUP_CORE_3 7
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/* config_noc */
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#define MASTER_GEM_NOC_CNOC 0
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#define MASTER_GEM_NOC_PCIE_SNOC 1
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#define SLAVE_AHB2PHY_0 2
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#define SLAVE_AHB2PHY_1 3
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#define SLAVE_AHB2PHY_2 4
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#define SLAVE_AHB2PHY_3 5
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#define SLAVE_ANOC_THROTTLE_CFG 6
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#define SLAVE_AOSS 7
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#define SLAVE_APPSS 8
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#define SLAVE_BOOT_ROM 9
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#define SLAVE_CAMERA_CFG 10
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#define SLAVE_CAMERA_NRT_THROTTLE_CFG 11
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#define SLAVE_CAMERA_RT_THROTTLE_CFG 12
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#define SLAVE_CLK_CTL 13
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#define SLAVE_CDSP_CFG 14
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#define SLAVE_CDSP1_CFG 15
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#define SLAVE_RBCPR_CX_CFG 16
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#define SLAVE_RBCPR_MMCX_CFG 17
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#define SLAVE_RBCPR_MX_CFG 18
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#define SLAVE_CPR_NSPCX 19
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#define SLAVE_CRYPTO_0_CFG 20
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#define SLAVE_CX_RDPM 21
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#define SLAVE_DISPLAY_CFG 22
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#define SLAVE_DISPLAY_RT_THROTTLE_CFG 23
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#define SLAVE_DISPLAY1_CFG 24
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#define SLAVE_DISPLAY1_RT_THROTTLE_CFG 25
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#define SLAVE_EMAC_CFG 26
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#define SLAVE_EMAC1_CFG 27
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#define SLAVE_GP_DSP0_CFG 28
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#define SLAVE_GP_DSP1_CFG 29
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#define SLAVE_GPDSP0_THROTTLE_CFG 30
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#define SLAVE_GPDSP1_THROTTLE_CFG 31
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#define SLAVE_GPU_TCU_THROTTLE_CFG 32
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#define SLAVE_GFX3D_CFG 33
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#define SLAVE_HWKM 34
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#define SLAVE_IMEM_CFG 35
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#define SLAVE_IPA_CFG 36
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#define SLAVE_IPC_ROUTER_CFG 37
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#define SLAVE_LPASS 38
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#define SLAVE_LPASS_THROTTLE_CFG 39
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#define SLAVE_MX_RDPM 40
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#define SLAVE_MXC_RDPM 41
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#define SLAVE_PCIE_0_CFG 42
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#define SLAVE_PCIE_1_CFG 43
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#define SLAVE_PCIE_RSC_CFG 44
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#define SLAVE_PCIE_TCU_THROTTLE_CFG 45
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#define SLAVE_PCIE_THROTTLE_CFG 46
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#define SLAVE_PDM 47
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#define SLAVE_PIMEM_CFG 48
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#define SLAVE_PKA_WRAPPER_CFG 49
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#define SLAVE_QDSS_CFG 50
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#define SLAVE_QM_CFG 51
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#define SLAVE_QM_MPU_CFG 52
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#define SLAVE_QUP_0 53
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#define SLAVE_QUP_1 54
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#define SLAVE_QUP_2 55
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#define SLAVE_QUP_3 56
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#define SLAVE_SAIL_THROTTLE_CFG 57
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#define SLAVE_SDC1 58
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#define SLAVE_SECURITY 59
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#define SLAVE_SNOC_THROTTLE_CFG 60
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#define SLAVE_TCSR 61
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#define SLAVE_TLMM 62
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#define SLAVE_TSC_CFG 63
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#define SLAVE_UFS_CARD_CFG 64
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#define SLAVE_UFS_MEM_CFG 65
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#define SLAVE_USB2 66
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#define SLAVE_USB3_0 67
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#define SLAVE_USB3_1 68
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#define SLAVE_VENUS_CFG 69
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#define SLAVE_VENUS_CVP_THROTTLE_CFG 70
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#define SLAVE_VENUS_V_CPU_THROTTLE_CFG 71
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#define SLAVE_VENUS_VCODEC_THROTTLE_CFG 72
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#define SLAVE_DDRSS_CFG 73
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#define SLAVE_GPDSP_NOC_CFG 74
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#define SLAVE_CNOC_MNOC_HF_CFG 75
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#define SLAVE_CNOC_MNOC_SF_CFG 76
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#define SLAVE_PCIE_ANOC_CFG 77
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#define SLAVE_SNOC_CFG 78
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#define SLAVE_BOOT_IMEM 79
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#define SLAVE_IMEM 80
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#define SLAVE_PIMEM 81
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#define SLAVE_PCIE_0 82
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#define SLAVE_PCIE_1 83
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#define SLAVE_QDSS_STM 84
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#define SLAVE_TCU 85
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/* dc_noc */
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#define MASTER_CNOC_DC_NOC 0
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#define SLAVE_LLCC_CFG 1
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#define SLAVE_GEM_NOC_CFG 2
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/* gem_noc */
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#define MASTER_GPU_TCU 0
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#define MASTER_PCIE_TCU 1
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#define MASTER_SYS_TCU 2
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#define MASTER_APPSS_PROC 3
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#define MASTER_COMPUTE_NOC 4
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#define MASTER_COMPUTE_NOC_1 5
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#define MASTER_GEM_NOC_CFG 6
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#define MASTER_GPDSP_SAIL 7
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#define MASTER_GFX3D 8
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#define MASTER_MNOC_HF_MEM_NOC 9
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#define MASTER_MNOC_SF_MEM_NOC 10
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#define MASTER_ANOC_PCIE_GEM_NOC 11
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#define MASTER_SNOC_GC_MEM_NOC 12
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#define MASTER_SNOC_SF_MEM_NOC 13
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#define SLAVE_GEM_NOC_CNOC 14
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#define SLAVE_LLCC 15
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#define SLAVE_GEM_NOC_PCIE_CNOC 16
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#define SLAVE_SERVICE_GEM_NOC_1 17
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#define SLAVE_SERVICE_GEM_NOC_2 18
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#define SLAVE_SERVICE_GEM_NOC 19
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#define SLAVE_SERVICE_GEM_NOC2 20
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/* gpdsp_anoc */
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#define MASTER_DSP0 0
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#define MASTER_DSP1 1
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#define SLAVE_GP_DSP_SAIL_NOC 2
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/* lpass_ag_noc */
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#define MASTER_CNOC_LPASS_AG_NOC 0
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#define MASTER_LPASS_PROC 1
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#define SLAVE_LPASS_CORE_CFG 2
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#define SLAVE_LPASS_LPI_CFG 3
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#define SLAVE_LPASS_MPU_CFG 4
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#define SLAVE_LPASS_TOP_CFG 5
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#define SLAVE_LPASS_SNOC 6
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#define SLAVE_SERVICES_LPASS_AML_NOC 7
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#define SLAVE_SERVICE_LPASS_AG_NOC 8
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/* mc_virt */
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#define MASTER_LLCC 0
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#define SLAVE_EBI1 1
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/*mmss_noc */
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#define MASTER_CAMNOC_HF 0
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#define MASTER_CAMNOC_ICP 1
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#define MASTER_CAMNOC_SF 2
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#define MASTER_MDP0 3
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#define MASTER_MDP1 4
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#define MASTER_MDP_CORE1_0 5
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#define MASTER_MDP_CORE1_1 6
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#define MASTER_CNOC_MNOC_HF_CFG 7
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#define MASTER_CNOC_MNOC_SF_CFG 8
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#define MASTER_VIDEO_P0 9
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#define MASTER_VIDEO_P1 10
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#define MASTER_VIDEO_PROC 11
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#define MASTER_VIDEO_V_PROC 12
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#define SLAVE_MNOC_HF_MEM_NOC 13
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#define SLAVE_MNOC_SF_MEM_NOC 14
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#define SLAVE_SERVICE_MNOC_HF 15
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#define SLAVE_SERVICE_MNOC_SF 16
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/* nspa_noc */
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#define MASTER_CDSP_NOC_CFG 0
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#define MASTER_CDSP_PROC 1
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#define SLAVE_HCP_A 2
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#define SLAVE_CDSP_MEM_NOC 3
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#define SLAVE_SERVICE_NSP_NOC 4
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/* nspb_noc */
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#define MASTER_CDSPB_NOC_CFG 0
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#define MASTER_CDSP_PROC_B 1
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#define SLAVE_CDSPB_MEM_NOC 2
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#define SLAVE_HCP_B 3
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#define SLAVE_SERVICE_NSPB_NOC 4
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/* pcie_anoc */
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#define MASTER_PCIE_0 0
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#define MASTER_PCIE_1 1
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#define SLAVE_ANOC_PCIE_GEM_NOC 2
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/* system_noc */
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#define MASTER_GIC_AHB 0
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#define MASTER_A1NOC_SNOC 1
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#define MASTER_A2NOC_SNOC 2
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#define MASTER_LPASS_ANOC 3
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#define MASTER_SNOC_CFG 4
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#define MASTER_PIMEM 5
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#define MASTER_GIC 6
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#define SLAVE_SNOC_GEM_NOC_GC 7
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#define SLAVE_SNOC_GEM_NOC_SF 8
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#define SLAVE_SERVICE_SNOC 9
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#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H */
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