34 lines
897 B
C
34 lines
897 B
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Intel Low Power Subsystem PWM controller driver */
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#ifndef __PLATFORM_DATA_X86_PWM_LPSS_H
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#define __PLATFORM_DATA_X86_PWM_LPSS_H
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#include <linux/types.h>
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struct device;
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struct pwm_lpss_chip;
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struct pwm_lpss_boardinfo {
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unsigned long clk_rate;
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unsigned int npwm;
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unsigned long base_unit_bits;
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/*
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* Some versions of the IP may stuck in the state machine if enable
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* bit is not set, and hence update bit will show busy status till
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* the reset. For the rest it may be otherwise.
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*/
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bool bypass;
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/*
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* On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device
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* messes with the PWM0 controllers state,
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*/
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bool other_devices_aml_touches_pwm_regs;
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};
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struct pwm_lpss_chip *devm_pwm_lpss_probe(struct device *dev, void __iomem *base,
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const struct pwm_lpss_boardinfo *info);
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#endif /* __PLATFORM_DATA_X86_PWM_LPSS_H */
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