121 lines
3.9 KiB
C
121 lines
3.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* IXP4XX cpu type detection
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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*/
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#ifndef __SOC_IXP4XX_CPU_H__
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#define __SOC_IXP4XX_CPU_H__
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#include <linux/io.h>
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#include <linux/regmap.h>
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#ifdef CONFIG_ARM
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#include <asm/cputype.h>
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#endif
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/* Processor id value in CP15 Register 0 */
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#define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */
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#define IXP42X_PROCESSOR_ID_MASK 0xffffffc0
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#define IXP43X_PROCESSOR_ID_VALUE 0x69054040
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#define IXP43X_PROCESSOR_ID_MASK 0xfffffff0
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#define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */
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#define IXP46X_PROCESSOR_ID_MASK 0xfffffff0
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/* Feature register in the expansion bus controller */
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#define IXP4XX_EXP_CNFG2 0x2c
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/* "fuse" bits of IXP_EXP_CFG2 */
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/* All IXP4xx CPUs */
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#define IXP4XX_FEATURE_RCOMP (1 << 0)
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#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
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#define IXP4XX_FEATURE_HASH (1 << 2)
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#define IXP4XX_FEATURE_AES (1 << 3)
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#define IXP4XX_FEATURE_DES (1 << 4)
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#define IXP4XX_FEATURE_HDLC (1 << 5)
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#define IXP4XX_FEATURE_AAL (1 << 6)
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#define IXP4XX_FEATURE_HSS (1 << 7)
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#define IXP4XX_FEATURE_UTOPIA (1 << 8)
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#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
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#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
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#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
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#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
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#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
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#define IXP4XX_FEATURE_PCI (1 << 14)
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#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
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#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
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#define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \
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IXP4XX_FEATURE_USB_DEVICE | \
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IXP4XX_FEATURE_HASH | \
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IXP4XX_FEATURE_AES | \
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IXP4XX_FEATURE_DES | \
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IXP4XX_FEATURE_HDLC | \
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IXP4XX_FEATURE_AAL | \
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IXP4XX_FEATURE_HSS | \
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IXP4XX_FEATURE_UTOPIA | \
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IXP4XX_FEATURE_NPEB_ETH0 | \
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IXP4XX_FEATURE_NPEC_ETH | \
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IXP4XX_FEATURE_RESET_NPEA | \
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IXP4XX_FEATURE_RESET_NPEB | \
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IXP4XX_FEATURE_RESET_NPEC | \
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IXP4XX_FEATURE_PCI | \
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IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
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IXP4XX_FEATURE_XSCALE_MAX_FREQ)
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/* IXP43x/46x CPUs */
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#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
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#define IXP4XX_FEATURE_USB_HOST (1 << 18)
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#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
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#define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \
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IXP4XX_FEATURE_ECC_TIMESYNC | \
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IXP4XX_FEATURE_USB_HOST | \
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IXP4XX_FEATURE_NPEA_ETH)
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/* IXP46x CPU (including IXP455) only */
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#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
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#define IXP4XX_FEATURE_RSA (1 << 21)
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#define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \
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IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
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IXP4XX_FEATURE_RSA)
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#ifdef CONFIG_ARCH_IXP4XX
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#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
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IXP42X_PROCESSOR_ID_VALUE)
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#define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
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IXP42X_PROCESSOR_ID_VALUE)
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#define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
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IXP43X_PROCESSOR_ID_VALUE)
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#define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
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IXP46X_PROCESSOR_ID_VALUE)
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static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
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{
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u32 val;
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regmap_read(rmap, IXP4XX_EXP_CNFG2, &val);
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/* For some reason this register is inverted */
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val = ~val;
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if (cpu_is_ixp42x_rev_a0())
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return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
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IXP4XX_FEATURE_AES);
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if (cpu_is_ixp42x())
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return val & IXP42X_FEATURE_MASK;
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if (cpu_is_ixp43x())
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return val & IXP43X_FEATURE_MASK;
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return val & IXP46X_FEATURE_MASK;
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}
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#else
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#define cpu_is_ixp42x_rev_a0() 0
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#define cpu_is_ixp42x() 0
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#define cpu_is_ixp43x() 0
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#define cpu_is_ixp46x() 0
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static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
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{
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return 0;
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}
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#endif
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#endif /* _ASM_ARCH_CPU_H */
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