75 lines
1.9 KiB
C
75 lines
1.9 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2017-2021 Intel Corporation. All rights reserved.
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*
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* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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*/
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#ifndef __SOF_INTEL_ATOM_H
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#define __SOF_INTEL_ATOM_H
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/* DSP memories */
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#define IRAM_OFFSET 0x0C0000
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#define IRAM_SIZE (80 * 1024)
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#define DRAM_OFFSET 0x100000
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#define DRAM_SIZE (160 * 1024)
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#define SHIM_OFFSET 0x140000
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#define SHIM_SIZE_BYT 0x100
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#define SHIM_SIZE_CHT 0x118
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#define MBOX_OFFSET 0x144000
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#define MBOX_SIZE 0x1000
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#define EXCEPT_OFFSET 0x800
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#define EXCEPT_MAX_HDR_SIZE 0x400
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/* DSP peripherals */
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#define DMAC0_OFFSET 0x098000
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#define DMAC1_OFFSET 0x09c000
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#define DMAC2_OFFSET 0x094000
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#define DMAC_SIZE 0x420
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#define SSP0_OFFSET 0x0a0000
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#define SSP1_OFFSET 0x0a1000
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#define SSP2_OFFSET 0x0a2000
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#define SSP3_OFFSET 0x0a4000
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#define SSP4_OFFSET 0x0a5000
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#define SSP5_OFFSET 0x0a6000
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#define SSP_SIZE 0x100
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#define STACK_DUMP_SIZE 32
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#define PCI_BAR_SIZE 0x200000
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#define PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32)
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/*
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* Debug
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*/
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#define MBOX_DUMP_SIZE 0x30
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/* BARs */
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#define DSP_BAR 0
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#define PCI_BAR 1
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#define IMR_BAR 2
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irqreturn_t atom_irq_handler(int irq, void *context);
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irqreturn_t atom_irq_thread(int irq, void *context);
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int atom_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
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int atom_get_mailbox_offset(struct snd_sof_dev *sdev);
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int atom_get_window_offset(struct snd_sof_dev *sdev, u32 id);
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int atom_run(struct snd_sof_dev *sdev);
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int atom_reset(struct snd_sof_dev *sdev);
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void atom_dump(struct snd_sof_dev *sdev, u32 flags);
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struct snd_soc_acpi_mach *atom_machine_select(struct snd_sof_dev *sdev);
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void atom_set_mach_params(struct snd_soc_acpi_mach *mach,
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struct snd_sof_dev *sdev);
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extern struct snd_soc_dai_driver atom_dai[];
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#endif
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