59 lines
1.7 KiB
C
59 lines
1.7 KiB
C
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// Copyright (c) 2022 Mediatek Corporation. All rights reserved.
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//
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// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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// Tinghan Shen <tinghan.shen@mediatek.com>
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//
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// Hardware interface for mt8186 DSP code loader
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#include <sound/sof.h>
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#include "mt8186.h"
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#include "../../ops.h"
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void mt8186_sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr)
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{
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/* set RUNSTALL to stop core */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
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RUNSTALL, RUNSTALL);
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/* enable mbox 0 & 1 IRQ */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_MBOX_IRQ_EN,
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DSP_MBOX0_IRQ_EN | DSP_MBOX1_IRQ_EN,
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DSP_MBOX0_IRQ_EN | DSP_MBOX1_IRQ_EN);
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/* set core boot address */
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snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVEC_C0, boot_addr);
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snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVECSEL, ADSP_ALTVECSEL_C0);
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/* assert core reset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
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SW_RSTN_C0 | SW_DBG_RSTN_C0,
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SW_RSTN_C0 | SW_DBG_RSTN_C0);
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/* hardware requirement */
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udelay(1);
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/* release core reset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
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SW_RSTN_C0 | SW_DBG_RSTN_C0,
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0);
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/* clear RUNSTALL (bit31) to start core */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
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RUNSTALL, 0);
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}
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void mt8186_sof_hifixdsp_shutdown(struct snd_sof_dev *sdev)
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{
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/* set RUNSTALL to stop core */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
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RUNSTALL, RUNSTALL);
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/* assert core reset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
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SW_RSTN_C0 | SW_DBG_RSTN_C0,
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SW_RSTN_C0 | SW_DBG_RSTN_C0);
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}
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