163 lines
6.7 KiB
C
163 lines
6.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra210_admaif.h - Tegra ADMAIF registers
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*
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* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA_ADMAIF_H__
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#define __TEGRA_ADMAIF_H__
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#define TEGRA_ADMAIF_CHANNEL_REG_STRIDE 0x40
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/* Tegra210 specific */
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#define TEGRA210_ADMAIF_LAST_REG 0x75f
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#define TEGRA210_ADMAIF_CHANNEL_COUNT 10
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#define TEGRA210_ADMAIF_RX_BASE 0x0
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#define TEGRA210_ADMAIF_TX_BASE 0x300
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#define TEGRA210_ADMAIF_GLOBAL_BASE 0x700
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/* Tegra186 specific */
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#define TEGRA186_ADMAIF_LAST_REG 0xd5f
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#define TEGRA186_ADMAIF_CHANNEL_COUNT 20
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#define TEGRA186_ADMAIF_RX_BASE 0x0
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#define TEGRA186_ADMAIF_TX_BASE 0x500
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#define TEGRA186_ADMAIF_GLOBAL_BASE 0xd00
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/* Global registers */
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#define TEGRA_ADMAIF_GLOBAL_ENABLE 0x0
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#define TEGRA_ADMAIF_GLOBAL_CG_0 0x8
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#define TEGRA_ADMAIF_GLOBAL_STATUS 0x10
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#define TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS 0x20
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#define TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS 0x24
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/* RX channel registers */
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#define TEGRA_ADMAIF_RX_ENABLE 0x0
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#define TEGRA_ADMAIF_RX_SOFT_RESET 0x4
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#define TEGRA_ADMAIF_RX_STATUS 0xc
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#define TEGRA_ADMAIF_RX_INT_STATUS 0x10
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#define TEGRA_ADMAIF_RX_INT_MASK 0x14
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#define TEGRA_ADMAIF_RX_INT_SET 0x18
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#define TEGRA_ADMAIF_RX_INT_CLEAR 0x1c
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#define TEGRA_ADMAIF_CH_ACIF_RX_CTRL 0x20
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#define TEGRA_ADMAIF_RX_FIFO_CTRL 0x28
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#define TEGRA_ADMAIF_RX_FIFO_READ 0x2c
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/* TX channel registers */
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#define TEGRA_ADMAIF_TX_ENABLE 0x0
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#define TEGRA_ADMAIF_TX_SOFT_RESET 0x4
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#define TEGRA_ADMAIF_TX_STATUS 0xc
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#define TEGRA_ADMAIF_TX_INT_STATUS 0x10
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#define TEGRA_ADMAIF_TX_INT_MASK 0x14
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#define TEGRA_ADMAIF_TX_INT_SET 0x18
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#define TEGRA_ADMAIF_TX_INT_CLEAR 0x1c
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#define TEGRA_ADMAIF_CH_ACIF_TX_CTRL 0x20
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#define TEGRA_ADMAIF_TX_FIFO_CTRL 0x28
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#define TEGRA_ADMAIF_TX_FIFO_WRITE 0x2c
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/* Bit fields */
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#define PACK8_EN_SHIFT 31
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#define PACK8_EN_MASK BIT(PACK8_EN_SHIFT)
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#define PACK8_EN BIT(PACK8_EN_SHIFT)
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#define PACK16_EN_SHIFT 30
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#define PACK16_EN_MASK BIT(PACK16_EN_SHIFT)
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#define PACK16_EN BIT(PACK16_EN_SHIFT)
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#define TX_ENABLE_SHIFT 0
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#define TX_ENABLE_MASK BIT(TX_ENABLE_SHIFT)
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#define TX_ENABLE BIT(TX_ENABLE_SHIFT)
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#define RX_ENABLE_SHIFT 0
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#define RX_ENABLE_MASK BIT(RX_ENABLE_SHIFT)
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#define RX_ENABLE BIT(RX_ENABLE_SHIFT)
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#define SW_RESET_MASK 1
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#define SW_RESET 1
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/* Default values - Tegra210 */
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#define TEGRA210_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300
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#define TEGRA210_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304
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#define TEGRA210_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000208
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#define TEGRA210_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000020b
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#define TEGRA210_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x0000020e
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#define TEGRA210_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000211
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#define TEGRA210_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000214
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#define TEGRA210_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000217
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#define TEGRA210_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021a
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#define TEGRA210_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021d
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#define TEGRA210_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300
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#define TEGRA210_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304
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#define TEGRA210_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x01800208
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#define TEGRA210_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0180020b
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#define TEGRA210_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x0180020e
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#define TEGRA210_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800211
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#define TEGRA210_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800214
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#define TEGRA210_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800217
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#define TEGRA210_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021a
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#define TEGRA210_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021d
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/* Default values - Tegra186 */
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#define TEGRA186_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300
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#define TEGRA186_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304
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#define TEGRA186_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000308
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#define TEGRA186_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000030c
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#define TEGRA186_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x00000210
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#define TEGRA186_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000213
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#define TEGRA186_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000216
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#define TEGRA186_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000219
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#define TEGRA186_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021c
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#define TEGRA186_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021f
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#define TEGRA186_ADMAIF_RX11_FIFO_CTRL_REG_DEFAULT 0x00000222
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#define TEGRA186_ADMAIF_RX12_FIFO_CTRL_REG_DEFAULT 0x00000225
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#define TEGRA186_ADMAIF_RX13_FIFO_CTRL_REG_DEFAULT 0x00000228
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#define TEGRA186_ADMAIF_RX14_FIFO_CTRL_REG_DEFAULT 0x0000022b
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#define TEGRA186_ADMAIF_RX15_FIFO_CTRL_REG_DEFAULT 0x0000022e
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#define TEGRA186_ADMAIF_RX16_FIFO_CTRL_REG_DEFAULT 0x00000231
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#define TEGRA186_ADMAIF_RX17_FIFO_CTRL_REG_DEFAULT 0x00000234
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#define TEGRA186_ADMAIF_RX18_FIFO_CTRL_REG_DEFAULT 0x00000237
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#define TEGRA186_ADMAIF_RX19_FIFO_CTRL_REG_DEFAULT 0x0000023a
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#define TEGRA186_ADMAIF_RX20_FIFO_CTRL_REG_DEFAULT 0x0000023d
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#define TEGRA186_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300
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#define TEGRA186_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304
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#define TEGRA186_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x02000308
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#define TEGRA186_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0200030c
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#define TEGRA186_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x01800210
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#define TEGRA186_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800213
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#define TEGRA186_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800216
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#define TEGRA186_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800219
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#define TEGRA186_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021c
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#define TEGRA186_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021f
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#define TEGRA186_ADMAIF_TX11_FIFO_CTRL_REG_DEFAULT 0x01800222
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#define TEGRA186_ADMAIF_TX12_FIFO_CTRL_REG_DEFAULT 0x01800225
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#define TEGRA186_ADMAIF_TX13_FIFO_CTRL_REG_DEFAULT 0x01800228
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#define TEGRA186_ADMAIF_TX14_FIFO_CTRL_REG_DEFAULT 0x0180022b
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#define TEGRA186_ADMAIF_TX15_FIFO_CTRL_REG_DEFAULT 0x0180022e
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#define TEGRA186_ADMAIF_TX16_FIFO_CTRL_REG_DEFAULT 0x01800231
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#define TEGRA186_ADMAIF_TX17_FIFO_CTRL_REG_DEFAULT 0x01800234
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#define TEGRA186_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT 0x01800237
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#define TEGRA186_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT 0x0180023a
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#define TEGRA186_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT 0x0180023d
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enum {
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DATA_8BIT,
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DATA_16BIT,
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DATA_32BIT
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};
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enum {
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ADMAIF_RX_PATH,
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ADMAIF_TX_PATH,
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ADMAIF_PATHS,
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};
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struct tegra_admaif_soc_data {
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const struct snd_soc_component_driver *cmpnt;
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const struct regmap_config *regmap_conf;
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struct snd_soc_dai_driver *dais;
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unsigned int global_base;
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unsigned int tx_base;
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unsigned int rx_base;
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unsigned int num_ch;
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};
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struct tegra_admaif {
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struct snd_dmaengine_dai_dma_data *capture_dma_data;
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struct snd_dmaengine_dai_dma_data *playback_dma_data;
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const struct tegra_admaif_soc_data *soc_data;
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unsigned int *mono_to_stereo[ADMAIF_PATHS];
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unsigned int *stereo_to_mono[ADMAIF_PATHS];
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struct regmap *regmap;
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};
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#endif
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