370 lines
10 KiB
C
370 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* RISC-V code
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*
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* Copyright (C) 2021 Western Digital Corporation or its affiliates.
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*/
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#include <linux/compiler.h>
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#include <assert.h>
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#include "kvm_util.h"
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#include "processor.h"
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#define DEFAULT_RISCV_GUEST_STACK_VADDR_MIN 0xac0000
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static uint64_t page_align(struct kvm_vm *vm, uint64_t v)
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{
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return (v + vm->page_size) & ~(vm->page_size - 1);
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}
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static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry)
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{
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return ((entry & PGTBL_PTE_ADDR_MASK) >> PGTBL_PTE_ADDR_SHIFT) <<
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PGTBL_PAGE_SIZE_SHIFT;
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}
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static uint64_t ptrs_per_pte(struct kvm_vm *vm)
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{
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return PGTBL_PAGE_SIZE / sizeof(uint64_t);
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}
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static uint64_t pte_index_mask[] = {
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PGTBL_L0_INDEX_MASK,
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PGTBL_L1_INDEX_MASK,
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PGTBL_L2_INDEX_MASK,
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PGTBL_L3_INDEX_MASK,
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};
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static uint32_t pte_index_shift[] = {
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PGTBL_L0_INDEX_SHIFT,
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PGTBL_L1_INDEX_SHIFT,
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PGTBL_L2_INDEX_SHIFT,
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PGTBL_L3_INDEX_SHIFT,
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};
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static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level)
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{
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TEST_ASSERT(level > -1,
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"Negative page table level (%d) not possible", level);
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TEST_ASSERT(level < vm->pgtable_levels,
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"Invalid page table level (%d)", level);
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return (gva & pte_index_mask[level]) >> pte_index_shift[level];
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}
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void virt_arch_pgd_alloc(struct kvm_vm *vm)
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{
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size_t nr_pages = page_align(vm, ptrs_per_pte(vm) * 8) / vm->page_size;
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if (vm->pgd_created)
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return;
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vm->pgd = vm_phy_pages_alloc(vm, nr_pages,
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KVM_GUEST_PAGE_TABLE_MIN_PADDR,
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vm->memslots[MEM_REGION_PT]);
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vm->pgd_created = true;
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}
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void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
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{
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uint64_t *ptep, next_ppn;
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int level = vm->pgtable_levels - 1;
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TEST_ASSERT((vaddr % vm->page_size) == 0,
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"Virtual address not on page boundary,\n"
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" vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size);
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TEST_ASSERT(sparsebit_is_set(vm->vpages_valid,
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(vaddr >> vm->page_shift)),
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"Invalid virtual address, vaddr: 0x%lx", vaddr);
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TEST_ASSERT((paddr % vm->page_size) == 0,
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"Physical address not on page boundary,\n"
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" paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size);
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TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
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"Physical address beyond maximum supported,\n"
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" paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
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paddr, vm->max_gfn, vm->page_size);
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ptep = addr_gpa2hva(vm, vm->pgd) + pte_index(vm, vaddr, level) * 8;
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if (!*ptep) {
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next_ppn = vm_alloc_page_table(vm) >> PGTBL_PAGE_SIZE_SHIFT;
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*ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) |
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PGTBL_PTE_VALID_MASK;
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}
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level--;
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while (level > -1) {
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ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) +
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pte_index(vm, vaddr, level) * 8;
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if (!*ptep && level > 0) {
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next_ppn = vm_alloc_page_table(vm) >>
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PGTBL_PAGE_SIZE_SHIFT;
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*ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) |
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PGTBL_PTE_VALID_MASK;
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}
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level--;
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}
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paddr = paddr >> PGTBL_PAGE_SIZE_SHIFT;
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*ptep = (paddr << PGTBL_PTE_ADDR_SHIFT) |
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PGTBL_PTE_PERM_MASK | PGTBL_PTE_VALID_MASK;
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}
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vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
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{
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uint64_t *ptep;
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int level = vm->pgtable_levels - 1;
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if (!vm->pgd_created)
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goto unmapped_gva;
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ptep = addr_gpa2hva(vm, vm->pgd) + pte_index(vm, gva, level) * 8;
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if (!ptep)
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goto unmapped_gva;
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level--;
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while (level > -1) {
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ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) +
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pte_index(vm, gva, level) * 8;
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if (!ptep)
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goto unmapped_gva;
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level--;
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}
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return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1));
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unmapped_gva:
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TEST_FAIL("No mapping for vm virtual address gva: 0x%lx level: %d",
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gva, level);
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exit(1);
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}
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static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent,
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uint64_t page, int level)
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{
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#ifdef DEBUG
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static const char *const type[] = { "pte", "pmd", "pud", "p4d"};
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uint64_t pte, *ptep;
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if (level < 0)
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return;
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for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) {
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ptep = addr_gpa2hva(vm, pte);
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if (!*ptep)
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continue;
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fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "",
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type[level], pte, *ptep, ptep);
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pte_dump(stream, vm, indent + 1,
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pte_addr(vm, *ptep), level - 1);
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}
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#endif
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}
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void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
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{
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int level = vm->pgtable_levels - 1;
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uint64_t pgd, *ptep;
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if (!vm->pgd_created)
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return;
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for (pgd = vm->pgd; pgd < vm->pgd + ptrs_per_pte(vm) * 8; pgd += 8) {
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ptep = addr_gpa2hva(vm, pgd);
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if (!*ptep)
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continue;
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fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "",
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pgd, *ptep, ptep);
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pte_dump(stream, vm, indent + 1,
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pte_addr(vm, *ptep), level - 1);
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}
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}
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void riscv_vcpu_mmu_setup(struct kvm_vcpu *vcpu)
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{
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struct kvm_vm *vm = vcpu->vm;
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unsigned long satp;
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/*
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* The RISC-V Sv48 MMU mode supports 56-bit physical address
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* for 48-bit virtual address with 4KB last level page size.
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*/
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switch (vm->mode) {
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case VM_MODE_P52V48_4K:
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case VM_MODE_P48V48_4K:
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case VM_MODE_P40V48_4K:
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break;
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default:
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TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode);
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}
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satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN;
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satp |= SATP_MODE_48;
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vcpu_set_reg(vcpu, RISCV_CSR_REG(satp), satp);
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}
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void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
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{
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struct kvm_riscv_core core;
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vcpu_get_reg(vcpu, RISCV_CORE_REG(mode), &core.mode);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc), &core.regs.pc);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.ra), &core.regs.ra);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.sp), &core.regs.sp);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.gp), &core.regs.gp);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.tp), &core.regs.tp);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t0), &core.regs.t0);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t1), &core.regs.t1);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t2), &core.regs.t2);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s0), &core.regs.s0);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s1), &core.regs.s1);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a0), &core.regs.a0);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a1), &core.regs.a1);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a2), &core.regs.a2);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a3), &core.regs.a3);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a4), &core.regs.a4);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a5), &core.regs.a5);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a6), &core.regs.a6);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7), &core.regs.a7);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s2), &core.regs.s2);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s3), &core.regs.s3);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s4), &core.regs.s4);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5), &core.regs.s5);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s6), &core.regs.s6);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s7), &core.regs.s7);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s8), &core.regs.s8);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s9), &core.regs.s9);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10), &core.regs.s10);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11), &core.regs.s11);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t3), &core.regs.t3);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t4), &core.regs.t4);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t5), &core.regs.t5);
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vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t6), &core.regs.t6);
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fprintf(stream,
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" MODE: 0x%lx\n", core.mode);
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fprintf(stream,
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" PC: 0x%016lx RA: 0x%016lx SP: 0x%016lx GP: 0x%016lx\n",
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core.regs.pc, core.regs.ra, core.regs.sp, core.regs.gp);
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fprintf(stream,
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" TP: 0x%016lx T0: 0x%016lx T1: 0x%016lx T2: 0x%016lx\n",
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core.regs.tp, core.regs.t0, core.regs.t1, core.regs.t2);
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fprintf(stream,
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" S0: 0x%016lx S1: 0x%016lx A0: 0x%016lx A1: 0x%016lx\n",
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core.regs.s0, core.regs.s1, core.regs.a0, core.regs.a1);
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fprintf(stream,
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" A2: 0x%016lx A3: 0x%016lx A4: 0x%016lx A5: 0x%016lx\n",
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core.regs.a2, core.regs.a3, core.regs.a4, core.regs.a5);
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fprintf(stream,
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" A6: 0x%016lx A7: 0x%016lx S2: 0x%016lx S3: 0x%016lx\n",
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core.regs.a6, core.regs.a7, core.regs.s2, core.regs.s3);
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fprintf(stream,
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" S4: 0x%016lx S5: 0x%016lx S6: 0x%016lx S7: 0x%016lx\n",
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core.regs.s4, core.regs.s5, core.regs.s6, core.regs.s7);
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fprintf(stream,
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" S8: 0x%016lx S9: 0x%016lx S10: 0x%016lx S11: 0x%016lx\n",
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core.regs.s8, core.regs.s9, core.regs.s10, core.regs.s11);
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fprintf(stream,
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" T3: 0x%016lx T4: 0x%016lx T5: 0x%016lx T6: 0x%016lx\n",
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core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6);
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}
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static void __aligned(16) guest_unexp_trap(void)
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{
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sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT,
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KVM_RISCV_SELFTESTS_SBI_UNEXP,
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0, 0, 0, 0, 0, 0);
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}
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struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
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void *guest_code)
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{
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int r;
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size_t stack_size;
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unsigned long stack_vaddr;
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unsigned long current_gp = 0;
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struct kvm_mp_state mps;
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struct kvm_vcpu *vcpu;
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stack_size = vm->page_size == 4096 ? DEFAULT_STACK_PGS * vm->page_size :
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vm->page_size;
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stack_vaddr = __vm_vaddr_alloc(vm, stack_size,
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DEFAULT_RISCV_GUEST_STACK_VADDR_MIN,
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MEM_REGION_DATA);
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vcpu = __vm_vcpu_add(vm, vcpu_id);
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riscv_vcpu_mmu_setup(vcpu);
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/*
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* With SBI HSM support in KVM RISC-V, all secondary VCPUs are
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* powered-off by default so we ensure that all secondary VCPUs
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* are powered-on using KVM_SET_MP_STATE ioctl().
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*/
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mps.mp_state = KVM_MP_STATE_RUNNABLE;
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r = __vcpu_ioctl(vcpu, KVM_SET_MP_STATE, &mps);
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TEST_ASSERT(!r, "IOCTL KVM_SET_MP_STATE failed (error %d)", r);
|
||
|
|
|
||
|
|
/* Setup global pointer of guest to be same as the host */
|
||
|
|
asm volatile (
|
||
|
|
"add %0, gp, zero" : "=r" (current_gp) : : "memory");
|
||
|
|
vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.gp), current_gp);
|
||
|
|
|
||
|
|
/* Setup stack pointer and program counter of guest */
|
||
|
|
vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_vaddr + stack_size);
|
||
|
|
vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code);
|
||
|
|
|
||
|
|
/* Setup default exception vector of guest */
|
||
|
|
vcpu_set_reg(vcpu, RISCV_CSR_REG(stvec), (unsigned long)guest_unexp_trap);
|
||
|
|
|
||
|
|
return vcpu;
|
||
|
|
}
|
||
|
|
|
||
|
|
void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...)
|
||
|
|
{
|
||
|
|
va_list ap;
|
||
|
|
uint64_t id = RISCV_CORE_REG(regs.a0);
|
||
|
|
int i;
|
||
|
|
|
||
|
|
TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n"
|
||
|
|
" num: %u\n", num);
|
||
|
|
|
||
|
|
va_start(ap, num);
|
||
|
|
|
||
|
|
for (i = 0; i < num; i++) {
|
||
|
|
switch (i) {
|
||
|
|
case 0:
|
||
|
|
id = RISCV_CORE_REG(regs.a0);
|
||
|
|
break;
|
||
|
|
case 1:
|
||
|
|
id = RISCV_CORE_REG(regs.a1);
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
id = RISCV_CORE_REG(regs.a2);
|
||
|
|
break;
|
||
|
|
case 3:
|
||
|
|
id = RISCV_CORE_REG(regs.a3);
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
id = RISCV_CORE_REG(regs.a4);
|
||
|
|
break;
|
||
|
|
case 5:
|
||
|
|
id = RISCV_CORE_REG(regs.a5);
|
||
|
|
break;
|
||
|
|
case 6:
|
||
|
|
id = RISCV_CORE_REG(regs.a6);
|
||
|
|
break;
|
||
|
|
case 7:
|
||
|
|
id = RISCV_CORE_REG(regs.a7);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
vcpu_set_reg(vcpu, id, va_arg(ap, uint64_t));
|
||
|
|
}
|
||
|
|
|
||
|
|
va_end(ap);
|
||
|
|
}
|
||
|
|
|
||
|
|
void assert_on_unhandled_exception(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
}
|